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Technology Stocks : ADI: The SHARCs are circling! -- Ignore unavailable to you. Want to Upgrade?

To: BMcV who wrote (2604)	1/12/2001 11:48:53 AM
From: Jim Oravetz	Read Replies (2) \| Respond to of 2882

Old news about ADI/INTC: DSP tries to bridge the gap By Chris Edwards, Electronics Times Dec 11, 2000 (10:18 AM) URL: electronicstimes.com Analog Devices and Intel have decided to use pipelining and design techniques from embedded microprocessors for a digital signal processor (DSP) that attempts to do the job of both types of architecture. The Micro Signal architecture is based on a classic DSP design with two multiply-accumulate units. But it adds support for multimedia in the form of single-instruction, multiple-data operations and design techniques normally found on general-purpose processors. Intel has brought in support for dynamic voltage and frequency scaling to reduce power when the processor is not fully loaded. Willie Anderson, director of DSP development for the Joint Development Design Centre, said: "Dynamic power management is an implementation issue. Any chip could implement it. Fundamentally, what the Micro Signal architecture brings forward is ease of use. It has byte addressability, which most DSPs don't have. It will have both C and C++ available." The main change made for the new architecture is in the pipeline. "It has a fully interlocked pipeline, which is not present in very-long instruction word DSPs," said Anderson. "The long interrupt latency that you find with DSPs is to do with them having unprotected [software-managed] pipelines. When they process inner loops, they have to disable interrupts, which leads to very long interrupt latencies. "Interlocked pipelines come at a cost but that cost has mostly been mitigated. The cost is a few gates in the control section and that does not scale in the same way as the datapath section." ++++++++++++++++++ FWIW, This last paragraph seems counter to my understanding of DSP vs. General purpose CPU's. Most DSP's would have less latency, not more. Both CPU's and DSP's have gotten more complex with multiple internal register banks that must be preserved before interrupt service routines are run. Jim