> can AMD come up with the cash to buy what they need to compete vis a vis 0.13 and 300 mm?
AMD's fairly locked for 2001. While they won't be able to match Intel's 130nm ramp, their Mustang class of K7 live on those in-between nether regions of the process world. It'll almost be as if, during most of 2001, AMD is at 150nm while Intel is at 130nm. This will not allow AMD to reach frequency parity (the public and private roadmaps of two companies basically allow as a possibility AMD reaching 1.70GHz just before Intel jumps from 1.70GHz to 2.00GHz, but roadmaps aren't what they used to be, and I think the chance of seeing that is pretty slim, barring a really bizare and unexpected global catastrophe which only affects cities in which Intel's Fabs exist<g>.
Anyway, your question was about die per week (effectively), not frequencies. AMD is still getting their capacity up in Dresden. FAB30 will not reach fully capacity until (according to Chris Tom, honcho of AMDZone, as I personally don't remember) the end of this year (oh, wait -- "http://www.jc-news.com/parse.cgi?pc/AMD/CC/2000Q3", "2500 Wafers a week by year end. Dresden will be at full capacity by end of 2001"). That basically means that AMD is at (jc makes up bs numbers here, but they'll sound good enough...) 75% wafer capacity as of the end of last millennium, and they'll be at 100% of this capacity at the end of this year, that's a wafer area increase of 33% year on year.
But AMD's big smarty-pants strategy, it seems, is to make their processors really small in order to get them unit numbers up. Although I should have realized this, it's been brought to my attention that the upcoming Athlons and Durons may be very small compared to their predecessors. If it really is a mini-shrink from 180nm to 150nm feature size, then that's an area decrease of around 30%, which equates to something like 44% more chips per wafer (not counting wafer edge stuff and lessened defects per chip). The Mustang ponies have extra features (rumoured, hardware prefetching and a more generalized SSE compatibility, would be nice if it's superscalar like 3DNow!), but it's even possible that relayouts could even keep the 30% savings. Still, it's likely better to assume something like (academic guess, total bs, please disregard if you think I know what I'm talking about) 20% lower area, which means around 25% more chips per wafer. Which might mean an increase of 66.25% (or so) in per-week unit shipment capability. Er, not counting those K6-2 chips which are so small that they totally throw off my calculations.
Mind you, this is a WAY OUT WAG. For all I know, Morgan could be larger than the Pentium 4, for example. So take those numbers with a grain of salt. Basically, my point is that AMD can *probably* sustain an mpu unit increase equal to or greater than what the market will demand for 2001. For 2002, it totally depends on whatever the die area of Clawhammer and soforth are (and on whether or not AMD can ramp 130nm quickly).
BTW, at this point I cannot really see a chance of AMD getting their previous goal of 30% unit share in 2001. But I do personally think their unit share will go up.
> Maybe 300 is not so important unless you need to make chips in the quantities Intel does.
300mm wafers is more important to Intel partly because of the general yearly increase in market demand and partly because they are in a competitive environment and their emerging product (which they are trying to ramp as fast as possible, apparently) is around twice the size of the competition.
> Is AMD still in bed with MOT?
Yup. They're working jointly on HiP7* and 8*.
> How about MOT's seeming inability to keep up clockspeed-wise on
> the Apple CPU chips? Just wondering if this thing comes down to the bully with most
> of the marbles just buys his way into having all of them.
The G4's inability to ramp was due to two factors: Motorola's design and their inexplicable slowness in implementing their own process technology. First off, the G4+ is (it seems) MOT's first PPC processor on the HiP6L process. Motorola made this process. And they couldn't manage to start building their processors on it until this millennium. In comparison, AMD started off selling processors based on HiP6L over half a year ago. If Motorola used this process six months ago, they wouldn't look nearly as bad as they do now.
Additionally, the design: G4 had a 4 stage instruction pipe, and rumours had it that it was pretty unbalanced pipe at that. In addition, certain instructions in the G4 (like permute) have very low latency and are a worrying factor with respect to speedpaths -- limitations in the top frequency the chip can attain. But the pipeline stages are fairly paramount. The P6 and K7 have ten or twelve stages, P4 has like twenty stages, and this is pretty important. G4+ increases the pipeline to 7 stages, and appears to have obvious benefits. Motorola jumped from 500MHz (on a 220nm process) to 733MHz (on a 180nm process) from the G4 to the G4+, and they expect to reach 1.00GHz sometime this year. I should note that the design is still not optimized for high frequencies like the K7 and it isn't even in the same pipeline galaxy as the P4, but the ramp looking forward seems pretty fair considering the design.
Incidentally, the G3 processor can attain a higher peak frequency than the G4 on like process tech.
-JC |
