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To: Petz who wrote (25633)1/18/2001 2:39:10 PM
From: Pravin KamdarRespond to of 275872
 
John,

The Q1 Palomino will be a notebook chip. Perhaps the first 1 GHz notebook chip from anybody. The 1.3 GHz in Q1 will be TBird (possibly 1.33 GHz/266 FSB also)

That was my interpretation from the CC, as well. Also, talk of 0.15u was pure speculation. I never considered it.

Pravin.



To: Petz who wrote (25633)1/18/2001 4:24:10 PM
From: dale_laroyRespond to of 275872
 
"I thought part of the power savings and scalability of the Palomino was going to come from using 0.15 vs. 0.18 design rules, but according to dale_laroy this is not the case. Is that a change?"

AMD never stated that Palomino would use 0.15-micron design rules. Indeed, the only mention by AMD of 0.15-micron design rules was for Duron (unspecified generation), and possibly Flash, at Fab25.

OTOH, until about two months ago, it was not explicitly stated that Palomino would use 0.18-micron design rules, so many, including myself, were expecting the use of 0.15-micron design rules. Actually, I figured AMD would implement 0.15-micron step & scan equipment at Fab30, then move this used equipment to Fab25 when Fab30 was upgraded with 0.13-micron step & scan equipment.