SI
SI
discoversearch

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor.  We ask that you disable ad blocking while on Silicon Investor in the best interests of our community.  If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.
Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Joseph Pareti who wrote (125500)1/18/2001 5:28:01 PM
From: Tenchusatsu  Respond to of 186894
 
Joe, <do you think they will keep the p4 L1 cache at 8k or do you see a chance to upgrade it>

I have absolutely no idea. Personally, I'd like to see that L1d cache increased, but that might be too tall of an order, especially if it changes latencies, pipeline structure, timing dependencies, etc. Then again, back when Intel made the transition from Pentium Pro to Pentium II, the L1d cache was increased from 8K to 16K with seemingly no impact to clock speed, so I guess it can be done.

My guess is that for Northwood (Pentium 4 on 0.13u), Intel will leave the L1 cache alone. Then Intel will let high clock speeds carry Northwood beyond anything the competition can even hope for, both in GHz and in overall performance.

Tenchusatsu



To: Joseph Pareti who wrote (125500)1/18/2001 5:30:17 PM
From: Scumbria  Respond to of 186894
 
Joseph,

The P4 L1 cache is probably stuck at 8K because of it's (low latency) two-cycle access time. This severely restricts the cache size, and any increase in cache size would impact clock speed.

The Athlon architects used a large three-cycle cache, which is obviously the intelligent thing to do.

Scumbria
p4stinks@hotmail.com


HomeMailHotSubjectMarksPeopleMarksKeepersSettings
Terms Of UseContact UsCopyright/IP PolicyPrivacy PolicyAbout UsFAQAdvertise on SI
© 2025 Knight Sac Media.  Data provided by Twelve Data, Alpha Vantage, and CityFALCON News