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To: Dealer who wrote (30157)	1/29/2001 9:43:23 AM
From: Dealer	Read Replies (1) \| Respond to of 65232

RMBS--Rambus Demonstrates High-Speed Chip Connection Technologies at DesignCon Includes First Public Demonstration of 3.125 Gbps Quad SerDes Cell LOS ALTOS, Calif.--(BUSINESS WIRE)--Jan. 29, 2001--Rambus Inc. (Nasdaq:RMBS - news) today announced it will demonstrate multiple chip connection technologies in the Rambus booth no. 123 at DesignCon 2001. DesignCon will host the first public demonstration of Rambus' 3.125 Gbps Quad Serializer/Deserializer (SerDes) Cell for use in high-speed networks. In addition, Rambus engineers will demonstrate QRSL(TM) and RSL technologies and present technical papers. Rambus will demonstrate bit-error-rate measurement techniques for high-speed serial links using Agilent's error performance analyzer. Model development and memory system design for QRSL and RSL technologies using Agilent's TDR and VNA equipment will also be demonstrated. 3.125 Quad SerDes Cell Rambus' Quad SerDes Cell allows a lower cost, simpler backplane connection with 25% greater performance at lower power than alternative stand-alone SerDes components. The Rambus® 3.125 Gbps Quad SerDes Cell can support the 10 Gbps full-duplex data rate popular in network line cards supporting OC48, OC192 and higher data rates over 30 inches of interconnect. The Rambus SerDes cell is implemented with low-cost standard CMOS processes. Demo 1: 3.125 Gbps Quad SerDes Cell Physical Features Quad links in a single core 1.0 to 3.125 Gbps data rate per link IP cell on foundry process 1.8V supply, 0.18u CMOS process Applications Gigabit/10 Gigabit Ethernet Infiniband(TM) Fibre Channel Router backplane links XAUI (4x 3.125 Gbps) SONET optical module interfaces Custom chip-to-chip applications Description The demonstration focuses on bit-error-rate measurement techniques for high-speed serial links using the Agilent 86130A error performance analyzer. Quad Rambus Signaling Levels (QRSL) QRSL(TM) technology enables data transfer rates of 1.6 Gb/sec, twice Rambus' current signaling technology. QRSL combines the patented double data rate (DDR) technology along with multi-level signaling to transfer four bits per clock cycle in order to achieve unprecedented commodity signaling rates of 1.6 Gbps, yielding 12.8 Gigabytes per second (GB/s) from a 64-bit bus. Demo 2: QRSL Technology Features 1.6 Gb/sec/pin single-ended parallel bus 400MHz clock x4 bits/clock cycle Multi-drop (1-4 devices) or point-to-point Presentation at ISSCC 2001 Description During the demonstration, the Agilent Infiniium(TM) 54845a oscilloscope is used to observe the transmitted signal. Demo 3: QRSL Signal Integrity Model Development Technical Motivation Simulation of high-speed signaling requires extremely accurate model Demonstration Deriving accurate SPICE model from TDR and VNA measurements Prototype 1.6 Gb/sec/pin multi-level parallel interface Description The high-performance Agilent TDR, Model 86100A is used to accurately characterize the loading effects of stub Via and a through Via. Optimization of the VNA data is used to build the SPICE model from DC to 2GHz. Rambus Presentation Tuesday, January 30 -- 4:00 p.m.-4:45 p.m. ``A 1.6 G-Bit/s/pin Multi-Level Parallel Interconnection'' Rambus Signaling Level (RSL) for RDRAM Rambus has helped to close the bandwidth gap created by the explosive Internet use and high-performance consumer products. In 1992, Rambus introduced Rambus Signaling Level (RSL) technology. RSL technology incorporated into RDRAM®s provided the semiconductor manufacturers with 10 times the bandwidth, or 500MHz, than was used in PCs at that time. The innovative signaling technology transferred one bit of information per clock edge. Today, RSL has been improved to operate at 800MHz on a long channel (with modules) and 1066MHz on a short channel (devices soldered to the motherboard). RDRAMs are ideal for small memory subsystems and chip-to-chip connections to solve performance bottlenecks in consumer, computer and communications products. These applications include multi-processor interconnect in servers, line cards, networking equipment, video games, HDTVs, set-top boxes, digital video recorders, and sealed box Information appliances. As bandwidth requirements increase, these markets will also ultimately be served by QRSL technology. Demo 4: Sony PlayStation®2 Memory Sub-System Features Workstation performance in a game console Dual Channel RDRAM Interface 3.2 GB/sec peak memory bandwidth 32MB RDRAM memory Reduced PCB area and cost Description High-speed clock and data signals are being measured on the Rambus Channel using the Agilent Infiniium(TM) 54845A oscilloscope with 2.5GHz active probes. Rambus Presentation Wednesday, January 31 -- 10:00 a.m.-10:50 a.m. ``Design of a 3.2 GB/sec memory sub-system for PlayStation®2'' About Rambus Inc. Rambus Inc. (Nasdaq:RMBS - news) is an intellectual property company that designs, develops and licenses high-bandwidth chip-connection technologies which enable semiconductor memory devices to keep pace with faster generations of processors and controllers. To date, these efforts have resulted in more than 100 U.S. and foreign patents issued to Rambus. Rambus has licensed its technology to approximately 30 semiconductor companies for the development, manufacture and sale of Rambus-compatible ICs. Providers of Rambus-based integrated circuits include the world's leading DRAM, ASIC, controller and microprocessor manufacturers. Note to Editors: Rambus and RDRAM are registered trademarks of Rambus Inc. QRSL is a trademark of Rambus Inc. PlayStation and the ``PS'' Family logo are registered trademarks of Sony Computer Entertainment Inc. Other trademarks that may be mentioned in this release are the intellectual property of their respective owners.