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To: Dan3 who wrote (126569)	2/4/2001 2:04:41 AM
From: Tenchusatsu	Respond to of 186894

Dan, <Cache tags must be invalidated for locations accessed by other processors in the uma node - this requires address bus bandwidth and isn't affected by larger caches.> Invalidation is ALWAYS better than reading and writing to main memory, which is what you have to do if you don't have enough cache space to store your data. Of course, as you add more cache, you get diminished returns, but that has nothing to do with invalidation and other cache coherency concerns. By the way, a 2-way SMP Athlon with 760MP chipset could really have used large processor caches because of the two point-to-point EV6 buses and the new MOESI protocol. But now that Mustang is cancelled, 760MP-based platforms will only shine in low-end 2P solutions. Lucky for you and the rest of the AMDroids, such a solution is rather popular these days. Tenchusatsu