Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (65392)	2/5/2001 5:35:03 PM
From: Jdaasoc	Read Replies (1) \| Respond to of 93625

carl: Since RSL and QRSL are dead dead dead already, I guess NEC is just piling on more dirt on the corpse. john eetimes.com NEC lays plans for Gbit interface ICs By Paul Kallender EE Times (02/05/01, 4:50 p.m. EST) TOKYO — As part of its push into high-speed interface communications devices, NEC Corp. on Monday (Feb. 5) announced it has developed a chip capable of 2.5-gigabit/second transfers per channel. While aimed at applications such as highly parallel computing, a senior NEC official hinted that the company could push the technology into CPU-memory interface applications. NEC developed a test chip last August that used 21 transmitters and receivers in full-duplex mode at 2.5 gigabits per channel, and also cut encode and decode signal transfer times to a third of present devices, according to Kazuyuki Nakamura, is principal researcher at NEC's Silicon Systems Research Laboratories. To achieve the 2.5-gigabit bandwidth per I/O, Nakamura said his team first overcame the devilish but delicate timing issues that arise over cable lengths between clocks through multiplexing by using a serial conversion circuit. Secondly, the team attacked the 40-nanosecond encoding-decoding delay by adding a control line on top of the chip's 20 transmission lines. This cut transmission time to 13 ns or 6.5 cycles, he said. "Forty nanoseconds or larger isn't so good for high-speed communications," Nakamura said. "We have reduced latency to a fraction." The NEC team also found a way to help signals shout over noise while keeping the chip's power at 1.5 volts. NEC has integrated an additional driver that reads and controls the amplitude of the waveforms in the IC's transmission lines, sending an amplitude control signal that boosts the signals, he said. Lastly, NEC has developed a very high precision control adjustment circuit that eliminates switching timing noise between coarse and fine control lines by using two fine delay lines that switch between each other at an optimal 20 picoseconds. "This is new," Nakamura said. "Usually the switching timing noise degrades precision timing. There's no switching between the lines now." Application chips based on the 2.5-Gbit device will be available in about a year, said Nakamura, who previewed the next-generation chip at a press briefing Monday (Feb. 5) in Tokyo, prior to the presentation of a paper at the International Solid-State Circuits Conference (ISSCC) in San Francisco. NEC is also presenting details of a 5-Gbit/s chip with an optical interface, and a "very experimental" 10-Gbit/s CMOS receiver technology, according to Masao Fukuma, general manager and principal researcher at NEC's Silicon Systems Research Laboratories (Sagamihara, Tokyo). While NEC has publicly stated its commitment to system-on-chip technologies, the company has also been pushing hard at interface speeds, Fukuma said. The combination of ISSCC papers represent the fruits of NEC's recent push to explode the bandwidth and speed of interface chips, Fukuma said. The company intends to develop test-level terabit-capable chips in 2005, he said. Behind these developments is NEC's fundamental belief that high-clocking approaches, for example that of Rambus Inc., will have difficulty scaling to meet impending needs. Instead, NEC believes in parallel processing architecture built around high-speed communication chips. "What we have now represents a very high level of integration. Users' requirements are becoming very aggressive. Rambus-type approaches may not be sufficient," Fukuma said. The chip will initially be aimed at applications in servers, new massively parallel computers, and much more, Fukuma said. Now that NEC considers 10-Gbit/s point-to-point interfacing technology feasible, the company may develop it beyond logic. "By using this technology, we hope to develop the next-generation interface between CPU and memory," Fukuma said. "This is now a candidate for the post-Rambus era."