>> Sequence Licenses Its Inductance Extraction Tool to QUALCOMM for Wireless Chip Design
February 05, 2001
Business Wire
Sequence Design, Inc., the specialist in power, timing and signal integrity optimization for system-on-chip (SOC) integrated circuits, today announced that QUALCOMM CDMA Technologies, a division of QUALCOMM Incorporated QCOM, will utilize the company's Columbus-RF(TM) RLC interconnect modeler in the design of radio-frequency (RF) integrated circuits for digital wireless applications.
After extensive evaluation, QUALCOMM chose to license the Sequence tool based on its ability to accurately model the parasitic inductance of wires on a chip and the ease of use of this software within the Cadence Analog Artist(TM) design tools.
At Gigahertz frequencies, the inductive behavior of a chip's interconnect is a critical consideration in determining whether or not the chip will meet its performance specifications. Without accurate advance knowledge of this behavior, design teams may fabricate RF chips that will not work correctly.
"Columbus-RF is the first tool we've seen that can accurately predict parasitic wire inductance," said Jim Tran, director of product management for QUALCOMM CDMA Technologies. "This capability translates directly to faster product development."
"QUALCOMM is at the absolute forefront of digital wireless design today," said Eric Filseth, vice president, product marketing for Sequence. "We're extremely pleased that QUALCOMM has chosen our solution."
About Columbus-RF(TM)
Columbus-RF(TM) is a state-of-the-art interconnect modeling tool used during the design of RF and other high-frequency analog integrated circuits, where layout parasitics are an important contributor to chip performance. Columbus-RF accurately models not only the resistance and capacitance of a chip's interconnect, but also leverages an advanced, patent-pending algorithm to calculate its inductance -- a critical property at Gigahertz frequencies.
Columbus-RF is seamlessly integrated into the popular Analog Artist(TM) and Diva(TM) design flow from Cadence Design Systems CDN, enabling push-button post-layout simulation of demanding RF, analog and mixed-signal designs.
Columbus-RF is a component of the Columbus Interconnect Modeling Suite, which provides design teams with a single interconnect modeling platform for entire "system-on-chip" designs which include analog and mixed-signal blocks. Sequence's patented Exact Topological Decomposition algorithm not only enables it to achieve the industry's highest interconnect modeling accuracy, but also scales efficiently in multiprocessing environments such as compute farms; this makes Columbus an ideal choice for very large designs.
Columbus-RF leverages technology libraries based on the Silicon Integration Initiative (Si2) SIPP standard, an industry format supported by leading foundries such as TSMC, UMC, Chartered Semiconductor and others.
About Sequence
Sequence Design, Inc. is the specialist in timing, power and signal integrity optimization for design closure of system-on-chip integrated circuits. Sequence's chip design software and services enable engineering teams to develop superior products quickly, in order to achieve competitive advantage in high-growth technology markets. Customers include Broadcom, Ericsson, Fujitsu, LSI Logic, NEC, Nokia, Nortel Networks, MMC Networks, Sony, Sun Microsystems, Texas Instruments, Toshiba and Vitesse Semiconductor.
Sequence supports worldwide development and field service operations. The company was formed through the merger of Sente, Inc. and Frequency Technology. Sequence is privately held; investors include Alpine Technology Ventures, Atlas Venture, Intel, IVP, LSI Logic, Menlo Ventures, Sigma Partners, Skywood Ventures, Sofinnova, and Sumitomo Corporation.
Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' MENT Open Door(TM) partnership programs. Please visit our web site at www.sequencedesign.com. <<
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