SiGe and CMOS battle over gigabit transceiver turf
By Rick Merritt
EE Times
(02/06/01, 12:47 p.m. EST)
SAN FRANCISCO — Racing to ratchet up the speed of the Internet's backbone, a handful of researchers detailed their latest gigabit-class transceivers to a standing-room only crowd at the International Solid-State Circuits Conference on Monday (Feb 5). Their work revealed a race that pits competing process technologies in a game of cost versus time-to-market.
Lucent Technologies and Hitachi Ltd. described how they leveraged silicon germanium to nail early 40- and 10-Gbit/second designs respectively, though both said power dissipation of their parts is higher than they would like. Broadcom Corp. and a research team from UCLA separately described 2.5- and 10-Gbit parts designed in standard CMOS that they claimed will offer lower power and lower cost as well as a smoother path to highly integrated components.
The packed hall sprinkled with attendees from newly minted optical startups indicated that optical networking remains one of the hottest topics in engineering today. But Rick Walker, principal project engineer with Agilent Technologies Inc. and chairman of the session, took a skeptical view.
Shipments are leveling off of the 100-Mbit/s Ethernet products now used as a standard link for business systems, and the follow-on gigabit devices described at the session will see significantly lower volume sales and profits because their use will be confined to backbone networks, Walker said. "We have built a tree from the leaves in, and what we are doing with 10 gigabit and beyond today is building the trunk, so I am not so bullish on this generation," he said.
In Walker's view devices using SiGe will have an edge because CMOS parts will show significant jitter on fibre lengths of 40 kilometers and beyond, where much of the 10- and 40-gigabit systems will ultimately be deployed, he said.
Lucent has already shipped prototype 40-Gbit/s time division multiplexing systems to MCI Worldcom and expects to ship production 40-Gbit/s TDM and wavelength division multiplexing systems by the end of the year, said Mario Reinhold, member of technical staff for Lucent's optical group in Nuremberg, Germany. Reinhold detailed a 40-Gbit/s clock and data recovery device built entirely in SiGe that would be at the heart of these systems.
He noted, however, that "at 5 watts, the power consumption is not where it should be. Starting this project in 1999, we didn't work to deliver low power consumption, but just to show that this is possible," Reinhold said.
Hitachi used a mixture of SiGe and CMOS to build a single chip 10-Gbit/s transceiver that complies with the OC-192 standard and should ship as a product by the end of the year. The 5.6 x 5.3 mm2 die consumes 2.6 W from a 3.3/2.5-V supply and comes in a 264-pin BGA, said Satoshi Ueno, an assistant senior engineer for Hitachi.
"The market demands a part with 2W dissipation now, but SiGe demands relatively high voltage," Ueno said. "It's a big problem. In the next release [which will also use a mix of SiGe and CMOS] we will have lower power," he said.
Power was not a problem for Newport Communications, recently acquired by Broadcom, which described an OC-48 (2.5 Gbit/s) transceiver made in 0.18-micron CMOS. The part dissipates 500 mW from a 1.8-V power supply, a thermal envelop which allows the part to fit in a 100-pin LQFP.
"One of our major goals with this design was to put an OC-48 transceiver in CMOS," said Afshin Momtaz, a principal design engineer at Broadcom (Irvine, Calif). "Then you can integrate it into an ASIC or add a lot of digital features. Also the power is much lower compared to parts in bipolar or GaAs so there is less heat, you can get it into a small package and thus on a smaller board. Basically all these things bring it down to a lower-cost solution," he said.
Integration was a key consideration for the part, which has been in production for the past several weeks. Newport had about 20 ASIC designers working on a network processor when the company was acquired by Broadcom. Momtaz is now helping integrate three of the transceivers on the net CPU, which Broadcom plans to launch later this year. Ultimately 16 of the transceivers could be put on a processor to support 40-Gbit/s throughput, the company said.
Pure CMOS was also the route taken by researchers from UCLA, who described a 10-Gbit/s clock and data recovery circuit, described by some as the most difficult piece of a fast transceiver design. The UCLA researchers are assisting about three companies in various stages of commercial 10-Gbit transceiver designs slated to ship starting later this year. And at least one company is working with the team to design a 40-Gbit/s part in CMOS.
"Using 0.18-micron CMOS, it turned out to be not too hard to design a 10-Gbit part," said Behzad Razavi, professor of electrical engineering at UCLA. "Forty gigabit is my next research idea. With 0.13-micron CMOS, we could do it. A lot of things will become attractive with that technology," he said.
Suppliers trying to catch the market quickly will not go with CMOS, but ultimately parts needing high levels of integration will not go with SiGe, Razavi said. "Power dissipation and integration favor CMOS, so you can put multiple transceivers on a chip," he said.
Not everyone in the ISSCC session audience agreed. SiGe is "not a show stopper, you can integrate all the way," said Ramin Shirani, vice president of engineering for Big Bear Networks (Milpitas, Calif.), a seven-month-old startup working on 40-Gbit and faster boards and systems.
"There are companies out there today with 0.16-micron SiGe processes that have no more than a 10 percent overhead over standard CMOS," Shirani said. "By mixing CMOS and SiGe, you can have blocks of 1.8-V and 1.5-V power supply on parts; that keeps power dissipation under control." |
