To: Dan3 who wrote (126882 ) 2/8/2001 1:51:41 PM From: Tenchusatsu Read Replies (1) | Respond to of 186894 Dan, first of all, a server isn't just a glorified network router. So the memory bandwidth is used for more than just PCI-to-memory accesses. But it seems that you and I agree on this point. <And if P4 isn't positively drowning its memory bus with prefetch traffic, then why is dual channel PC800 necessary to equal the performance of a PIII or Athlon with single channel PC133? Why can't even dual channel PC600 supply enough bandwidth?> Someone pointed this out to me a year and a half ago. PC600 RDRAM has even worse latency than PC800. Also, as Scumbria points out, bandwidth isn't the problem in a Pentium 4 system. Prefetch serves two purposes. One, it's necessary because a P4 cacheline is 128 bytes long, but the maximum burst length of a single FSB transaction is 64 bytes. So when the first transaction is seen on the FSB, the second transaction is anticipated to be right behind it. And two, prefetch helps make use of the extra memory bandwidth that would normally be wasted in the middle of non-bandwidth intensive tasks. It is unclear how useful prefetching really is on most applications. But hey, if the bandwidth is available, why not leave it on and hope that it can buy you an extra bit of performance? (By the way, the prefetch logic was borrowed from the 840 Carmel chipset, which is no surprise since the 850 is pretty much an upgraded 840.) <I'd be interested in an informed criticism but if all you can come up with is "Wrong" then never mind.> You pretty much assumed that false statements were true without even thinking about whether they made sense or not. All they deserved was "Wrong." Tenchusatsu