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To: AK2004 who wrote (127319)2/13/2001 4:02:59 PM
From: fingolfen  Read Replies (1) | Respond to of 186894
 
Yes... and that grammar school arithmetic involves a lot of incorrect assumptions. You're assuming twice the die size of the P3 (which is correct) and half the yield (which there is no credible evidence to show that the yield is depressed on the P4). That's where your entire scenario falls completely apart...

Why are you so focused on the bogus yield data? Of course, your entire hypothesis falls apart without it...

Depending on what stepping you're looking at, die size for the P3E (coppermine) ranges from ~95-115. Northwood should be roughly half the size of Willamette (which is ~217 giving a final die size of ~109)... so you're going to get as many Northwood die on one 200mm wafer as you get coppermine die on one 200mm wafer.

I don't see why you fail to understand that means the availability of the P4 on 200mm 0.13 micron will be equivalent to the P3 on 200mm 0.18 micron. I also fail to understand why you aren't concerned about Intel gaining a 30% COG advantage by migrating to 300mm over 2 years ahead of AMD...