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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tony Viola who wrote (127353)	2/13/2001 6:55:29 PM
From: Tenchusatsu	Respond to of 186894

Tony, <Does this guy go around quoting yields about any other semiconducor company? I seriously doubt it. I think he has an ax to grind.> Excellent point. I'd sure like to see this guy's estimates of AMD's yields on Athlon, or Sun's yields on UltraSparc III, or even Transmeta's yields on Crusoe. Tenchusatsu

To: Tony Viola who wrote (127353)	2/13/2001 8:42:56 PM
From: Dan3	Read Replies (1) \| Respond to of 186894

Tony - those are NOT bad yields. I posted on the topic a while ago, and was dismissed by all you Intellabees, so you weren't expecting those numbers - and evidently neither was CSFB. I am not a FAB person, but I've done enough reading to know the expected, baseline, normal difference in yields between two die, on the same process, is the difference of the squares of the die area. There are obviously all sorts of qualifiers to that, but that's where you start. Now consider that parts of P4 are running at 2.6 to 3GHZ on a .18 process, and the only surprise is that P4 yields aren't worse. If, when going from a 100mm2 die to a 217mm2 die, yields only dropped from 80% to 40%, it's almost too good to be true. But someone here, semicoeng or Elmer or someone else, claimed that P4 didn't use the most aggressive of Intel's processes - which might explain why yields dropped by about 50% instead of the "normal" approximately 57% that the straight die size difference would predict. Note that the number of die that fit on a wafer must be multiplied by the yield to get the number of good die. I kept posting that doubling the die size normally quarters the number of good die, all else being equal. I wasn't making that stuff up. If the CSFB numbers are accurate, Intel's FABs are doing great - but, as I posted before, P4 is a very expensive chip to produce compared to PIII, Celeron, Athlon, and Duron. Intel is probably going from about 225 good die per wafer on PIII/Celeron to about 52 good P4 die per wafer - which is normal and to be expected as I posted before. But somebody must have gotten those numbers to CSFB, they thought about the implications, and they became concerned. What's actually going on is that the percentage of bad die doubles while number of available die declines, but as a rough heuristic, that formula works. If the process initially yields very few bad die, then there is less of a diffence when the die size goes up. Frankly, even 50 good die per wafer is almost too good to be true - you guys should all calm down and realize that the market's slow and Intel has a heck of a lot of FAB space. But a big ramp of P4 on .18 is going to burn up a lot of wafers. Dan