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To: Scumbria who wrote (128150)2/23/2001 12:16:33 AM
From: Elmer  Respond to of 186894
 
Re: "It is pretty clear from the bus architecture of P4 that it was intended to mate to dual channel RDRAM"

You're right Scumbria. Intel never intended to evolve this design and certainly never intended to add more cache which might change things.

EP



To: Scumbria who wrote (128150)2/23/2001 2:20:15 AM
From: Tenchusatsu  Respond to of 186894
 
Scumbria, <It is pretty clear from the bus architecture of P4 that it was intended to mate to dual channel RDRAM.>

The Willamette/Foster bus is very similar to the P6 bus, and you can bet that the P6 bus wasn't originally designed for dual-channel RDRAM. What makes you say the Wmt bus is?

Tenchusatsu


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