Japan to launch separate nanometer-gate research project
By Paul Kallender
EE Times
(02/23/01 09:37 a.m. PST)
TOKYO — Major Japanese semiconductor makers, research laboratories and the Japanese government are planning to launch their own joint research into 70- and 50-nanometer gate technologies, similar to the cooperative effort of IMEC and International Sematech.
The seven year, two-phase fundamental research project, dubbed Mirai ("the future" in Japanese), will start April 1 and, depending on budget appropriations for the next fiscal year, should receive initial funding of about 3.8 billion yen ($32.7 million) to develop 70-nm node technology within three years. The project's second four-year phase will then attack 50-nm technology, according to Hideo Setoya, executive director of the Association of Super-Advanced Electronics Technologies (ASET), a government-industry umbrella organization responsible for coordinating the research.
Simultaneously, the Japanese government will also back a two-year initiative to study ways to lower semiconductor manufacturing costs by 60 percent. First year funding for this project, which will also start April 1, will be about $6.4 million, according to documents released by the New Energy Development Organization (NEDO), a technology sponsoring arm of the Ministry of Economy, Trade and Industry (METI). NEDO will have overall responsibility for both programs.
Details about which companies and laboratories will participate in Mirai are still being hammered out as industry and government work out the project's development schedule, said Setoya. While official details are scant, Mirai's basic structure has taken root, he said. Echoing the classic Japanese government-industry framework that powered Japanese semiconductor research in the 1970s, Mirai's funding will come from NEDO, and ASET will do the hands-on coordination and recruit participants.
On Thursday (Feb. 22) NEDO sponsored Mirai's first steering committee meeting with industry representatives from Fujitsu Ltd., Matsushita Electric and NEC Corp., and academic representatives from Tokyo, Keio, Osaka and other elite universities to decide how to warm up the project, according to Sadao Uemura, director of NEDO's electronic and information technology development department. "It's a big plan and METI has already decided to go ahead," he said.
NEDO will issue a formal request for proposals from participants in early March.
While the various agencies gear up to launch Mirai, the project itself faces three major issues, said Setoya: technology, money and coordination.
"There are many, many walls," he said. "The lithography is very important and difficult. If the 50-nm nodes must be ready by 2007, then we must have the tools available by 2005."
And while Setoya did not suggest that the Mirai project was underfunded, he said ASET was anxious to get the fullest budget appropriation possible.
"Of course, we can accelerate the speed if more money is put in," he said. "Of course we are asking for more!"
Programs criticized
The past few years have seen increasing criticism here of national technology programs sponsored by the Japanese government, coordinated by ministries, and realized by industry, for such programs' perceived failure to meet modern real-time business needs, internal wrangling, and lack of clear objectives. Earlier this month at the Industry Strategy Symposium Japan 2000, leading semiconductor and electronics company executives criticized this stasis approach. Rebuking what is sometimes called the "iron triangle" of government, bureaucrats and industry, Sony Corp. president Nobuyuki Idei called for more flexible approaches to create next-generation technologies and products.
More directly, Nippon Foundry Inc. president Yukio Sakamoto directly criticized Semiconductor Leading Edge Technologies Inc. (Selete), the METI-backed research project to develop system-on-chip technologies, and Asuka, a Mirai counterpart that seeks to develop process technologies beyond the 100-nm node, as potentially ineffective.
"There are 11 companies doing this [Asuka project]; that's a tall order," Sakamoto said. "The maximum number should be three. It will be very difficult to make this a success."
Responding to Sakamoto's comments at ISS, Setoya said, "Maybe it is a reaction to the perception of bureaucracy. We must avoid this and encourage and promote actual results." Setoya suggested that ASET was keenly aware of the need for efficient coordination between various agencies.
More pertinently, Setoya said, the Mirai program must deliver the results of each phase of its basic research to the Asuka program for implementation. ASET plans to sponsor joint meetings with Mirai and Asuka officials to adjust each parties' research programs, he said. The five-year Asuka project is due to deliver evaluations on 100-nm node technologies, including lithography, CAD and interconnect processes, in fiscal 2003.
"The important thing is that Mirai and Asuka will share the same lab so we hope the communication between them will be good," said Setoya.
Cooperation considered,/B>
Another important point will be the international sharing of research between Mirai and the separate IMEC-Sematech project, Setoya said. ASET is exploring what that cooperation will entail, but hopes to share some materials research and to exchange personnel. This cooperation will be addressed at the upcoming International Forum on Semiconductor Technology, to be held March 7-8 in Antwerp, Holland, co-sponsored by ASET, IMEC and Sematech.
Thursday's meeting at NEDO came ironically on the same day that Hitachi Ltd. announced it was joining IMEC and Sematech's effort on the same sub-70-nm research. Hitachi officials said the IMEC-Sematech approach would be faster and more productive than in-house research.
Hitachi officials were not available at press time to comment on the company's possible participation in Mirai, but Setoya said he was optimistic. "From the point of view of Hitachi, they may be making some kind of insurance," he said. |
