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Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Elmer who wrote (128226)	2/23/2001 8:22:28 PM
From: muzosi	Read Replies (1) \| Respond to of 186894

P4 has 20K L1 cache. 8K + 12K So you are assuming L1 and execution trace cache have completely exclusivity with respect to the lines they carry ? Probably average uop per x86 is around 3 given the way today's compilers generate simpler code so the sizes of "L1" cache and ET cache are very similar in terms of the number of instructions they can hold. I think it is a good assumption that there would be a very large overlap between the two. I like they way intel mentions this problem. They say "a line in level i doesn't imply it is also in level i+1". It doesn't imply but it most probably is especially for ET and "L1". ETC is mostly necessary to compensate for the fact that P4 x86 instruction decoder bandwidth is not enough and adding more decoders would've cost a lot more in area and power than adding the ETC. Muzo