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To: Tenchusatsu who wrote (128425)	2/27/2001 4:53:03 PM
From: Rob Young	Read Replies (1) \| Respond to of 186894

<How do you build a single server (not multiple systems) with 256 CPUs and a Terabyte of memory that scales?> "Simple. You chain a bunch of multi-CPU nodes together using a custom-designed interconnect. This is how Bull, Fujitsu, Hitachi, IBM's Numa-Q division (formerly Sequent here in Oregon), NEC, and Unisys plan on doing up to 64-way Merced/McKinley systems and beyond." ah ah ah.... very clearly laid out rules. After all, what is to keep anyone from chaining together a bunch of 256 CPU machines? With EV7 in mind, think about bandwidth and latency such that "remote" memory latency is very good indeed (details at www.alphapowered.com, see section on memory controller and number of cycles, also cpu to cpu router and cycles, etc.) <Hint: cache coherence is a problem beyond a certain point.> Yeah, as if cache coherence wasn't a problem for "simple" 4-way and 8-way SMP systems. "I personally wonder if you even realize the scope of the cache-coherency problem in super-scale systems. It goes way beyond the scope of the petty debate over McKinley vs. EV7 vs. Power4." Ummm.. know enough to be dangerous.. and also know there are very few ways to mask it as CPU count increases dramatically. The systems you describe above lean very heavily to NUMA while the EV7 machine looks more UMA than NUMA and programs are written as such... imagine that. Rob