Intel plans 4-bit-per-cell flash for mobile phones
By Anthony Cataldo
EE Times
(03/02/01, 3:19 p.m. EST)
SAN JOSE, Calif. — Despite the barriers keeping memory suppliers from making multibit-per-cell flash chips, Intel Corp. and would-be flash vendor Azalea Microelectronics Corp. are moving ahead to pack 4 bits in a cell, officials at both companies said.
While the task is daunting, Intel believes that upping its per-cell storage capacity within the next several years could be one way to keep the lid on ballooning flash memory prices.
Moore's Law dictates that flash density will double every year and a half. But users of flash memory — particularly cellular phone OEMs — are raising the amount of flash they consume at a rate that will more than double per-unit costs in three years.
Internet-ready wireless phones are already driving demand for bigger flash memory loads. The trend is most apparent in Japan, where cellular phone OEMs are putting an average of 42.7 Mbytes of flash memory into popular i-mode phones for NTT Docomo, said Curt Nichols, general manager of Intel's flash products group (Folsom, Calif.).
"By 2004, we think the average flash usage for cellular phones will be 100 Mbytes," said Nichols, speaking to a group of industry analysts at the Intel Developer Forum here this week. "If that happens, the bill-of-materials cost for flash, which was $6 per chip in 2000, will jump to $16. That's going to be tough to deal with."
A little bit
To further drive down the cost per bit, Nichols said Intel plans to introduce a 4-bit/cell flash device by 2003 or 2004. "At 2 bits per cell, you're moving down to the $10 level. At 4 bits per cell, we think we can drop that to the $8 level," he said.
Nichols noted, however, that the technical challenge is far from trivial. With its current Strataflash product, Intel took many years to figure out how to split the threshold voltage into four levels in order to read and write 2 bits of data in a single flash cell.
To do so, Intel had to develop ways to control the flow of electrons on the floating gate, sense the different voltage levels and reduce transistor leakage. There would be even less margin for error with a 4-bit/cell part — instead of four levels, you would need 16, Nichols said.
The voltage margin is determined by the delta between the programming and erase threshold voltage. Vendors are today working with a 3-V margin that they divide into four levels to read and write 2 bits. But with 4 bits, it will be exceedingly difficult to spread that 3 V across 16 levels, said Ali Pourkeramati, chief executive officer of Azalea (Santa Clara, Calif.).
Azalea, for its part, has come up with a way to get a better voltage margin by reducing the erase threshold voltage, giving it 5 V instead of 3 V to spread the 16 levels across. The trick, however, is reducing the erase threshold voltage "without going to depletion," Pourkeramati said. Patents covering the technology are pending, he said.
"The guys doing multibit flash are basically stuck at 2 bits and trying very hard to do it," he said. "For us, 4 bits is not a big deal."
Like Intel's, Azalea's multibit flash technology will be NOR-based and is targeted at code storage in cellular phones. The company's first 4-bit/cell flash products should appear on the market by the first half of 2003. A five-year-old nonvolatile-design house that has worked with companies like Cypress Semiconductor, Xilinx and Fairchild Semiconductor, Azalea plans to introduce its first flash devices later this year, starting with a single-chip flash-plus-E2PROM, Pourkeramati said.
Though multilevel-cell flash has been the subject of intense research among flash memory suppliers, few have been able to master even 2 bits per cell. One notable exception has been Intel, which introduced its 2-bit/cell Strataflash device in 1997 and is now shipping in densities as high as 128 Mbits. In the fourth quarter, Strataflash accounted for nearly a quarter of the flash memory bits Intel shipped, Nichols said.
A raft of changes must be made to the design, physical scaling and materials in order to make multilevel-cell flash devices. Secondarily, flash vendors have to make sure they do not infringe on existing patents, said Alan Niebel, managing director for Web-Feet Research Inc. (Monterey, Calif.). "There's a tremendous learning curve," Niebel said.
From a device-engineering standpoint, one of the hardest tasks is controlling transistor leakage. "The biggest challenge is spreading the threshold voltage over the arrays. Any kind of leakage on the bit line is going to kill you," said Pourkeramati.
Nevertheless, Niebel said, it's likely that companies like STMicroelectronics and Silicon Storage Technology will soon come out with their own NOR-based flash memory devices that can store 2 bits per cell.
Flash vendors not only must move to multilevel-cell storage to keep pace with direct competitors, but also to compete against companies pushing smaller-form-factor optical- and magnetic-storage devices. Ultra Card Inc., for example, is working on an IC card that will include a 2-Gbyte rotating magnetic disk, Niebel said.
The bottom line
"Flash is going to have to get down to 10 to 15 cents a megabyte in order to compete with these," Niebel said. "They're going to have to push the cost down, whatever it takes, whether it's Samsung moving to 0.13-micron process technology or Intel moving to 4 bits per cell."
In Intel's case, the process technology lags its processor road map. Last quarter, a small percentage of the flash devices the company shipped — about 3 million units — was manufactured on 0.18-micron process technology. This year, half the flash bits it ships should be manufactured on 0.18-micron design rules. The next process shrink will be 0.13 micron, which will come online in 2002 and ramp up steeply in 2003, Nichols said. |
