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To: Dan3 who wrote (30155)	3/3/2001 12:09:15 PM
From: Scumbria	Respond to of 275872

Dan, I thought about it some more, and with the large L1, the lack of critical word forwarding isn't such a big deal. Scumbria

To: Dan3 who wrote (30155)	3/3/2001 12:17:49 PM
From: fyodor_	Respond to of 275872

Dan: OTOH, I think it only discusses existing data in the L2 Yes, it discusses L2 transfers, where critical word first is supported. I don't think this has any implications for the DRAM transfers. -fyo

To: Dan3 who wrote (30155)	3/4/2001 3:13:44 AM
From: Petz	Respond to of 275872

It should be pretty easy to test if TBird has critical word first forwarding from DRAM. If you did very large memory accesses from low address to high address, the critical word would be identical to the first word in the cache line. But if you did memory access from the top to the bottom in reverse order, then the first word that the program accessed in a new cache line would NOT be the first word in the cache line. If both transfers take the same amount of time, the TBird supports critical-word-first access to DRAM. Petz