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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Paul Engel who wrote (30289)	3/5/2001 3:02:46 AM
From: Joe NYC	Read Replies (2) \| Respond to of 275872

Paul, That's where you and the AMDroids completely miss the point. A large L2 cache provides enormous system throughput improvements in SMP systems - ENORMOUS - by reducing traffic on the main memory bus. By virtue of its failure to increase the L2 cache beyond 256 K, AMD will be at a great technological disadvantage - and have to sell its CPUs at a huge discount to Intel's large L2 CPUs. Why is it that P4 doesn't offer more than 256K L2? Perhaps because it only addresses a single user single CPU desktop only - the same market as AMD? With realistic chance of selling CPUs to the server market, AMD will add more L2 cache. Re: "How can Intel charge more for the same chip when it goes to 4way box? " Because AMD WILL NOT have a 4-way system !!! I noticed something on Intel roadmap, where they distinguish Dual Processor and Multi Processor Foster. It looks like Intel is preparing for this situation. It seems like Intel is going nuts with the segmentations / fragmentation schemes. They have already GIVEN UP on that for the 760MP - or have you forgotten that? I think it will be a news to Tyan. I think you should e-mail them. Joe

To: Paul Engel who wrote (30289)	3/5/2001 7:59:17 AM
From: Dan3	Read Replies (1) \| Respond to of 275872

Re: A large L2 cache provides enormous system throughput improvements in SMP systems The benefits of a larger cache taper off as cache size increases. Intel's chips are limited to caching 12 pages per LSB, while AMD's chips can cache 20. Since all processes will normally start off with an LSB of 0x000, Intel processors can start thrashing the cache with as few as 12 active processes regardless of cache size, while AMD processors will always support a minimum of 20. The basic design of the Athlon core and cache architecture are more suited to server work than Intel's PIII/P4 architecture. Itanium actually reduces the set associativity from 12 to 10! Which may be one of the reasons why Itanium has been a disappointment, so far. While AMD SMP may never come (I've stopped waiting), if it does ever arrive, it may substantially outperform Xeon in application spaces with many threads. Dan