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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (30851)	3/8/2001 6:24:44 PM
From: fyodor_	Read Replies (1) \| Respond to of 275872

Scumbria: It is almost impossible to add new features to a 28 stage pipeline. I didn't quite mean it in that way... I firmly believe the amount of L2 cache will be doubled to 512kB. (Regarding L1: I "heard" that Intel engineers believe they can keep the L1 cache at 2 cycle access latency, partly because it is spatially located very, very close to the relevant units. Remember, the FP unit cannot access data in the L1 cache, but instead relies on the L2 cache.) Additionally, Intel might be able to cut out a bunch of unused transistors (all the "Jackson" stuff). If nothing else, this should lower the die size nicely. -fyo