To: charred water who wrote (67832 ) 3/15/2001 7:16:30 PM From: Bilow Read Replies (1) | Respond to of 93625 Hi charred water; Re definition of "bus" and the way the claims work... Cordob on MotleyFool has a good post on this with lots of explanation. It's a lot easier than reading through all the legal briefs. This is a very informative post, and I repeat it in total, with the original emphasis, and none of my own:Cordob, MotleyFool RMBS Thread #30947, March 15, 2001, 5:29PM For example, the most general claim that does not depend on the definition of "bus" is US05953263, claim 1: "A synchronous semiconductor memory device having at least one memory section which includes a plurality of memory cells, the memory device comprises: a programmable register to store a value which is representative of a delay time after which the memory device responds to a read request." I already started this kind of argument in post:boards.fool.com I do not agree that it is so simple , for one thing the summary of that '263' patent metions the bus, but Ok that's only a summary. What you claim here sounds simple, but it isn't. There has to be a confluence of timeline and claims. Now the '263' was applied for on december 9, 1996 That is too late, way later than the jedec stuff. Ok, but we have priority, see:This is a continuation of application Ser. No. 08/607,780, filed Feb. 27, 1996 now abandoned, which is a continuation of application Ser. No. 08/222,646, filed Mar. 31, 1994, which has issued as U.S. Pat. No. 5,513,327, which is a continuation of application Ser. No. 07/954,945, filed Sep. 30, 1992, which has issued as U.S. Pat. No. 5,319,755, which is a continuation of application Ser. No. 07/510,898, filed Apr. 18, 1990, now abandoned. So obviously the interesting one supporting the '263' patent is the '755' patent (filed sep. 1992):patent 5,319,755 Integrated circuit I/O using high performance bus interface This patent has as claim 1:(first part only)1. An apparatus for storing and retrieving data, wherein the apparatus comprises: (A) a first memory; (B) a second memory; (C) a multiline bus for coupling the first and second memories and for carrying control information, addresses, and the data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting one of the first and second memories without using any separate memory select line; That is clearly "the bus" I then read ALL the claims (59 of them) claims 2-16 refer to claim 1 (usually in the for "the apparatus of claim 1" etc.. further comprising) claim 17 is like claim 1 and contains the bus claim 18 ditto claims 19-32 refer back to claim 18 claim 33 contains the bus claims 34-59 refeer back to claim 33.Conclusion: in the 755 patent all claims refer to the bus (address and data combined) And: the '263' patent is based and claims priority as far as dates is concerned to this '755' patent. Even though some of the claims of '263' may not read "bus", they should if they want to claim priority back to 1992 (indirectly to 1990, the abandoned patent). Otherwise the '263' patent has been expanded. (illegal) I am not saying this is the whole story but I can see Infineon picking holes in at least that patent (one of the 4 in suit) cheers Corboards.fool.com -- Carl