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To: Scumbria who wrote (33454)3/25/2001 11:36:16 PM
From: dale_laroyRespond to of 275872
 
"Generally I prefer the concept of sophisticated compiler driven prefetching vs. dumb hardware prefetching."

Hardware prefetching need not be dumb. AMD has a patent on predictive cache prefetching that uses historical patterns to predict when prefetch will be useful, in much the same way that the Branch History Table is used to predict branches.

Even in the case of dumb hardware prefetch, cache flushing need not be much of a problem. As long as the prefetch only stays one cache line ahead of execution, it would have less impact than doubling the cache line size.

Personally, I would rather see AMD implement prefetch directly to L1, rather than to L2.



To: Scumbria who wrote (33454)3/26/2001 12:10:34 AM
From: Joe NYCRespond to of 275872
 
Scumbria,

Generally I prefer the concept of sophisticated compiler driven prefetching vs. dumb hardware prefetching.

But that's P4 approach. This means software companies releasing new, recompiled software (and the time lag associated with it) and users upgrading all their software to the latest versions (and the time lag associated with that). The end result is that the users may not get the benefit for 2 to 4 years.

"Dumb" hardware prefetching will benefit everyone buying the new processor immediately.

Joe