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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fyodor_ who wrote (33480)	3/26/2001 8:43:36 AM
From: Scumbria	Respond to of 275872

Fyo, The single-ported L1 cache on P4 allows only one access per cycle, which is inadequate for a superscalar CPU. The whole point of superscalar is to allow more than one instruction to execute simultaneously. If Intel throws in multithreading into the equation, they will further congest the cache access and lead to thrashing the tiny little data cache. wrt the in-order L1 access in K7, once again this has no impact on performance. If the cache hits, out-of-order is not needed. If the cache misses, out-of-order becomes important and is implemented in K7. The only major flaw I see in the K7 microarchitecture is that they put the address calculation and cache access in the execute stage. This should have been done earlier in the pipeline. Scumbria