Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Scumbria who wrote (33484)	3/26/2001 9:25:37 AM
From: fyodor_	Read Replies (1) \| Respond to of 275872

Scumbria: Compare K7 integer performance vs. PIII and P4. Do you really think they have a branch prediction problem? I don't have enough information to form an informed opinion on that - all I have to go by is other people's comments :/ Let me say this: I would need some benchmarks showing the performance of the CPUs (PIII/P4/K7) on code with varying amounts of branches. I'm not familiar with any such benchmarks online, so I don't really feel I have enough information to say. The only thing I will note is that considering that the Athlon has 3 integer pipelines, it doesn't do particularly well against the PIII. (but then this could easily be cache related or similar) If you don't see the BPU as needing an upgrade, what about the L2 cache? 11+ cycle access latency isn't exactly impressive. Would the Athlon see any serious benefit if this were lowered by a 2-3 cycles? What about the L1-L2 datapath? Yeah, so AMD says "what we have is good - we don't need the fancy stuff our competition has", but then that's what competing companies always say. Would the Athlon benefit from an increased L1-L2 bandwidth? What about increasing the number of operations the Athlon can keep in-flight, currently at 72? -fyo