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To: TimF who wrote (33536)	3/26/2001 5:05:53 PM
From: Scumbria	Read Replies (1) \| Respond to of 275872

Tim, Would making such a change in a future generation of processor break code that is highly optimized for the current processors? Is there any other potential downside of this change that you can think of? There aren't any software issues with making a change like that. It is strictly a pipeline change. The potential downside is that there is a larger branch miss penalty for register->register instructions (which are hardly ever used in x86.) In other words, it would be a very smart thing to do. Dirk basically copied the Alpha 21264 pipeline which was sensible for a RISC design, but not optimal for x86. Most x86 instructions access memory, so it makes sense to load the operands ahead of the execute stage. I would expect 20% IPC improvement from such a change, and it has no impact on clock speed. Scumbria