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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: porn_start878 who wrote (33848)	3/27/2001 10:24:48 PM
From: combjelly	Respond to of 275872

"Of what kind will be the memory bus, and will it cope with the impreesive i850 performance at, say 533MHz?" That is dependent on the memory hub being used. The beauty of that approach is that it is easier to do wide memory channels, since the memory hub can be located at the memory arrays. I suspect that you will eventually see several different types of memory hubs, some with L3 cache, and other without. Remember that LDT has up to 200Mbytes/second per pin, so the transfer to the CPUs can have more pines for more bandwidth.

To: porn_start878 who wrote (33848)	3/27/2001 11:10:15 PM
From: dale_laroy	Respond to of 275872

Initially, AMD wants to use HyperTransport to provide a hub for PCI and AGP devices. Long term however, AMD wants to create a new graphics standard whereby HyperTransport will replace both PCI and AGP. Keep in mind that HyperTransport is being promoted as a local networking protocol, so what are currently PCI devices could be viewed as network devices in a pure HyperTransport system. As for graphics, the GPU would become another node in the system, that would have its own local memory and access global system memory across HyperTransport just like another Hammer processor. would.

To: porn_start878 who wrote (33848)	3/27/2001 11:19:50 PM
From: Joe NYC	Read Replies (1) \| Respond to of 275872

Max, Of what kind will be the memory bus, and will it cope with the impreesive i850 performance at, say 533MHz? I think it will be whatever memory it uses. For example, if Hammer uses DDR, it will be a single channel of DDR, up to whatever speed it gets. If it ever gets to 400 MHz, it will be 3.2 GBs. But now, suppose you have a dual Sledge. Each will have it's own channel with bandwidth of 3.2 GB of local memory, plus, access to the far (remote, distant or whatever the term is) memory through LDT. Joe