Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: Joe NYC who wrote (33862)	3/27/2001 11:35:32 PM
From: THE WATSONYOUTH	Respond to of 275872

The deal between Cyrix and IBM was not just barter. It involved cash payments from Cyrix to IBM. The wafers with Cyrix design was part of the compensation, but not the only part, and not even a major part. IBM had an option to process additional wafers for their own use. I think it was assumed that IBM would do this to put these chips into their own computers, not to use the option to the fullest and flood the market. I have not seen the agreement so I don't know the details, but it was so horrible for Cyrix that NSM, after taking over Cyrix paid IBM a cash payment to terminate this contract. Again, it is hard for me to understand. From what you say, Cyrix contracts to IBM to fabricate wafers and pays for them. This is the main part of the deal. In addition, Cyrix grants IBM an option to process additional wafers for their own use. How many wafers??? For how long??? To be used how??? Only in IBM PCs?? To be sold on the open market at any price?? Under what assumptions by IBM?? By Cyrix?? Was this simply a "blank check"?? Again...these guys must have been morons. But you haven't seen the agreement either. Right?? Let's drop this. It's a waste of time. May Cyrix rest in peace. THE WATSONYOUTH

To: Joe NYC who wrote (33862)	3/28/2001 12:32:31 AM
From: dale_laroy	Read Replies (1) \| Respond to of 275872

Way back in 1995, I wrote a letter to AMD telling them that I thought their K5 processor was a white elephant. At that time, I suggested a four pronged attack to the problem of the K5. 1) Buy NexGen 2) Use the K5 design team to convert the Nx686 to a Pentium pin compatible design. 3) Hire one of the chief architects of the Alpha to lead the NexGen design team in producing a superpipelined x86 core with separate fp adder and fp multiplier units so that up to one fp add and one fp multiply could be launched every cycle, and coordinate with DEC to define a common bus interface for the Alpha and this future generation x86 core. 4) Abandon the K5, instead licensing the Cyrix 6x86 and 5x86 designs to be produced at Fab25. I figured that the 6x86 would have a smaller die size and higher speed grade yield than the K5, so AMD could simply sell the extra die per wafer to Cyrix at just the cost of packaging. It seems AMD paralleled the first three suggestions, but did not pursue the fourth. I wonder how things would have played out for AMD and Cyrix if they had pursued a variant of the fourth fork in this strategy. I based my initial suggestion on the die sizes that AMD and Cyrix were claiming for their respective processors at that time. As it turns out, even the 5k86 (which actually seems to be the variant described in Byte Magazine) had a die size of only 181mm2 @ 0.35-micron using 4ML. By contrast, the 5ML 6x86 had a die size of 169mm2, and would have very likely have been 25% larger using AMD's 4ML process technology (of course, with a 5ML processor ready to go, it might have been easier for AMD to have upgraded to 5ML than to for Cyrix to have layed out the 6x86 for 4ML). Anyway, the 6x86 was capable of reaching 100 MHz (not just PR100) at 0.65-micron using 3ML. The Pentium needed 4ML to reach this clock speed. My guess is that, had AMD been the foundry for the 6x86 instead of IBM, the 6x86 would have been able to scale linearly in speed grade from 0.65-micron, and if there had been a 4ML variant at 0.65-micron, it would have been shippable at 110 MHz. Thus, even before the shrink to 0.30-micron, AMD might have been able to have produced a 200 MHz 6x86 processor. Indeed, it may very well have been that, by June of 1996, the peak speed grade (not PR rating) 6x86 processors produced by AMD could have been matching the peak speed grade of Intel's own Pentium. Why do I think the 6x86 might have been able to scale linearly from 0.65-micron (SGS/IBM process) to 0.35-micron using AMD's process technology? Because AMD was able to scale their 486 core speed grade linearly to 0.35-micron, versus Intel's peak speed grade for the 486DX2 at 0.8-micron. AMD was able to ship a 120 MHz DX4 processor using 3ML @ 0.44-micron design rules. Linear scaling would have predicted 133 MHz at 0.4-micron, so a 10% lower shipping speed grade at 10% larger design rules is very close to linear. And this pattern held with the 0.35-micron Am5x86. I think AMD might have done quite well selling 6x86 processors versus Intel's same MHz Pentium, while providing perhaps 10% of the production to Cyrix at just the cost of packaging. And, because Cyrix would have been paying a pittance for those processors that they would be selling, it might have been quite profitable for Cyrix as well.