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To: fyodor_ who wrote (34278)3/30/2001 2:59:36 PM
From: Joe NYCRespond to of 275872
 
Fyo,

My understanding is that Clawhammer will be connected to an off-die Northbridge using LDT.

For some reason, I never even considered that possibility, which actually may be th way it will happen. The reason I never considered is because if the ultimate goal is to have the northbridge on the die, this presents too many intermediate steps and I mentally rejected it (probably prematurely).

Looking at the slide on the bottom of this page: viahardware.com you may be right. This memory controller / hub is likely going to be one serious piece of hardware (or actually silicon) 4 fairly fat LDT connections, plus probably 2 channels of DDR memory. The reason I say 2 channels is because the slide says capacity of 32 DIMMs, and there are only 4 memory controllers, and my ghess is that it is 4 DIMMs per channel. This kind of system would offer the ultimate flexibility to the server manufacturer.

But there are namy problems that I see with this:
- it does nothing about latency of memory access.
- it fails to address mainstream and low end.
- very little if any cost saving.
- too much of a pie in the sky technology which will go completely wo waste if the server penetration remains low.
- the memory controller / LDT hub has way too much complexity - 4 LDT connection plus memory controller.

Withe northbridge on die, you would number of advantages:
- only 1 LDT connection coming out of the CPU.northbridge die
- memory access close to the CPU - excellent latency
- connect this thing to a southbridge, you have low end / mainstream computer, at much cheaper price / reduced complexity.
- separate 4 to 6 way hub/switch - a discrete component that can be made buy the network guys creates a 4 way system, and since the device is doing only 1 thing, the high volume and simplicity will drive the price down

So the argument is what is better, merging memory controller with LDT hub, or with CPU die, and the answer is obvious to me - with the CPU die, where it provides solid performance benefit, at cost of the linkage to the particular memory type.

Joe

Joe