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To: Elmer who wrote (131380)3/30/2001 9:52:47 PM
From: Scumbria  Respond to of 186894
 
Elmer,

With hardware emulation of a chipset you can use the real thing, it terms of the peripherals. Also an RTL model is never as good as a gate level model because of timing effects.

Emulators don't give any timing information. They are useful only as functional simulators.

They are not the real thing because the netlist is generic, and not associated with any technology.

You really have no idea what you are talking about.

Scumbria



To: Elmer who wrote (131380)3/30/2001 10:33:17 PM
From: muzosi  Read Replies (1) | Respond to of 186894
 
Also an RTL model is never as good as a gate level model because of timing effects

It would indeed be a very broken design if your timing, especially at the boundary, changes after you do your synthesis and layout. Most of what's involved in those activities is "meeting timing". Also emulation is not for "timing" but for speed. Timing always changes between your fpga based emulation and the standard cell process.

Muzo


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