Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Amkor Technology Inc (AMKR) -- Ignore unavailable to you. Want to Upgrade?

To: Berk who wrote (935)	4/6/2001 12:52:35 PM
From: tech101	Read Replies (1) \| Respond to of 1056

The significance of 3D-SiP is not limited to the technology itself. In order to put different types of dies together to reduce size, the solution of 3D-SiP has become more and more popular. However, every chip company is focusing on a special area. It is difficult for a communication chip maker to do memory chips. Thus, more and more device makers and even chip makers have to rely on the specialized assemly and package companies like Amkor. Amkor sees no limit to stacking chips in 3-D packages By J. Robert Lineback Semiconductor Business News (04/04/01 14:49 p.m. EST) CHANDLER, Ariz. -- Amkor Technology Inc. here today (April 4) disclosed an aggressive lineup and roadmap for three-dimensional "stacked" chip packaging technologies, which are capable of housing three or more semiconductors and passive devices inside a single "system-in-package" product. Amkor's expanding portfolio of 3-D packages and assembly services are aimed at an exploding market for stacked and "side-by-side" chip package formats. According to market researcher TechSearch International Inc., stacked-chip package shipments will approach 230 million units in 2001, and volumes will grow 50% to 348 million units in 2002. Most of the stacked-chip packages today are used in mobile phones and wireless systems to save space by combining memory chips together in 3-D packages. However, 3-D packages are also growing as a low-cost alternative to system-on-chip (SoC) designs, said Amkor officials. Instead of integrating embedded memory or DRAM on processors and ASICs, more IC companies are moving to stacked packages as a way to keep the functions separate on different chips, according to Jon Woodyard, vice president of stacked chip-scale packaging at Amkor in Chandler. This multi-die approach, he said, enables processor and ASIC suppliers to use off-the-shelf commodity memories, and they can more quickly introduce custom versions of products for niche markets without launching a new IC design. The growth of mixed-signal and analog functions on ASICs and processors is also expanding the potential use of system-in-package (SiP) products as an alternative to single-die system-on-chip designs, Woodyard noted. He said separate devices for analog and logic functions enable suppliers to separately migrate those circuits to new process technologies on different roadmaps. Amkor has been shipping 3-D chip packages since 1999, and it has developed a variety of packaging types for stacking chips three or more high inside packages. Amkor also has packaging technology for placement of multiple chips next to each other--side-by-side. Leadframes and a variety of substrate packages are also available for 3-D packaging. Amkor is also offering both wirebond and flip-chip assembly of stacked and side-by-side 3-D packages. The company has deployed of its range of 3-D packaging technologies at high-volume assembly plants in South Korea and the Philippines, and it plans to put the capabilities in its new facilities in China and Taiwan, said Woodyard. "We have plans in place to proliferate those technologies," he said. "If we invest $100 million in China facility, the relative increase to add technology associated with stacking would be relatively minor--a few percentage points [on top of the basic assembly line]. It is not like adding a whole new facility for stacking," Woodyard added. Amkor believes it is one of the first chip-assembly contractors to offer volume 3-D stacking capabilities for three chips in a package. The three-high stacking technologies have been available for years in captive facilities in Japan, but it is just now moving into contract assembly houses, he said. "It is still a small market niche, focused mainly on memory," Woodyard said, referring to stacking of three chips in a package. "It's probably about 10% of the entire stacking business. We are just now engaging customers [for volume production services]." Amkor sees no limit to the number of chips that can be stacked inside a single package. But when multiple chips are packaged together, design considerations must be made early in IC development, Woodyard cautioned. "That has to be designed in from the very beginning because of the complexity of three-die stacking vs. just two," he said, referring to interconnection of chips in the package as well as final test. A major requirement for stacking three or more chips in a package is backside grinding of wafers to make them thin. "As we get down to the 2-mil back-grinding of wafers, you can go to three, four or five [die] stacking. It is virtually limitless in terms of stacking, as long as you can effectively route it on a substrate and wirebond it out," he said. In the 3-D packages, wafer thinning and thin substrates are used to achieve 1.4-mm height for three-die stacks and 1.2-mm for two-die stacks. Weight of stacked packages can be up to 70% less than multiple single-die packages. The cost of three-die stacked packages could be as much as 35% less than the cost of separate single die packages, according to Amkor. For the system maker, 3-D chip packages can reduce the board space by 30-to-60% compared to single-chip packages. siliconstrategies.com