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To: Gary Ng who wrote (131862)	4/7/2001 12:17:49 AM
From: Elmer	Respond to of 186894

Talking about P6 bus, are there any new things coming out for P7 ? As the P6 bus seems to be a revolutionary one comparing to P5 and is a huge success. Just wondering what will accompany the new P7 generation People are realizing now just how great a design the P6 split transaction bus is and how revolutionary it was back in '95 when it first appeared. Experts at the time trashed it in much the same way some "experts" here on this thread trash the P4 yet it supports SMP flawlessly from Celerons all the way up to 64 way Xeon systems. Meanwhile AMD can't get SMP to work in a measly 2-way with the EV6 bus architecture after years of trying. EV6 was touted as far more advanced than the P6 bus by the "experts" when AMD bought a license to use it. The P6 bus was simply over their heads then and the P4 is over their heads now. Don't expect the "experts" to understand for a couple more years. EP

To: Gary Ng who wrote (131862)	4/7/2001 12:32:09 AM
From: Tenchusatsu	Read Replies (1) \| Respond to of 186894

Gary, <Talking about P6 bus, are there any new things coming out for P7> Differences between P6 and Willamette/Foster bus: 1) Wmt bus quad-pumps data, P6 bus doesn't. 2) Cacheline size (i.e. normal burst transfer) is 64 bytes for Wmt bus, 32 bytes for P6 bus. 3) Wmt bus allows for one request every two clock cycles, P6 bus allows one request every three. 4) Wmt bus data is parity-protected (for some odd reason), P6 bus is ECC-protected. 5) Other minor differences. And that's about it. Tenchusatsu