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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: fyodor_ who wrote (35548)	4/12/2001 11:13:19 AM
From: dale_laroy	Respond to of 275872

"However, the performance advantage would be very significant. I hope AMD can do it..." The performance advantage would be so great that DDR SDRAM with an integrated memory controller would almost certainly outperform DDR-II with an external memory controller. Thus, even if the transition could be made faster with an external memory controller, the internal memory controller with old technology would be superior. One other thing. Clawhammer is rumored to have 512KB of L2 cache, yet the die size is not all that much greater than the estimate for Thoroughbred. Indeed, my own estimate for Thoroughbred's die size with 512KB of L2 cache exceeds AMD's claim for Clawhammer (not taking into consideration that Palomino is apparently significantly larger than TBird). When Motorola moved from an external PMMU to an integrated PMMU with the transition from 68020 to 68030, they claimed that the die area needed to integrate the PMMU was less than that needed for just the interface to the external PMMU. It may very well be that AMD is discovering the same thing about integrating the NB. It may very well be that the reason for the large die size of Timna was not the integrated NB, but the integrated video alone.

To: fyodor_ who wrote (35548)	4/12/2001 11:48:31 AM
From: Petz	Read Replies (2) \| Respond to of 275872

fyo, DaleWhat could become a negative is that during the transition AMD would have to produce multiple variants of the same processor. That is to say, when DDR-II is introduced, AMD will have to continue to offer Clawhammer with a DDR interface... The extra die space to continue to support regular DDR along with DDR-II is probably insignificant. The problem will be getting DDR-II right the first time, but if the DDR-II interface proved buggy, at least these chips could still support DDR. BTW, I noticed something new on my 1.33 AXIA -- the motherboard reports on the microcode download level on the bootup screen. AMD must have increased the re-programmability of the microcode on the AXIA stepping. Returning to the original integrated Northbridge idea, is there a way to make most of the northbridge section an FCPGA which is programmed after the rest of the die has been manufactured? Petz