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To: fyodor_ who wrote (37537)4/26/2001 9:15:09 PM
From: combjellyRespond to of 275872
 
"Will AMD use the Black Diamond lowK dielectric for the bulk-Si .13µ process?"

Likely. Low-k dielectrics are something that JS has mentioned as a big stumbling block for 0.13 micron. Black Diamond is certainly that, and can't be all that expensive if TSMC uses it also.



To: fyodor_ who wrote (37537)4/26/2001 11:23:04 PM
From: dale_laroyRead Replies (1) | Respond to of 275872
 
"Will AMD use the Black Diamond lowK dielectric for the bulk-Si .13µ process?
Will the process be as aggressive as the SOI process?"

My guess is no and possibly yes. AMD has never mentioned low-k dielectrics outside of the context of SOI. Low-k dielectrics would not only make the transition to bulk silicon more difficult, but decrease yields as well. Chances are that they could not squeeze a higher speed grade out of low-k dielectrics before the SOI launch. OTOH, even before the SOI launch, low-k dielectrics could probably yield somewhat lower power consumption for a given speed grade. Perhaps AMD will get experience with low-k dielectrics before SOI by using low-k dielectrics in mobile Thoroughbred.

My guess is that you will see volume shipments of mobile Thoroughbred in Q1 2002, volume shipments of desktop Thoroughbred and mobile Appaloosa in Q2 2002, volume shipment of mobile Barton and desktop Appaloosa in Q3 2002, and volume shipment of desktop Barton in Q4 2002.

Thus, by the end of 2002 the competition should be:

Northwood vs desktop Barton(SOI) and Clawhammer(SOI)
Willamette(or 0.18-micron relayout) vs desktop Thoroughbred
Tualatin vs Appaloosa w/128 L2 cache
Celeron vs Appaloosa(Morgan?) w/64K L2 cache
mobile Tualatin vs mobile Barton & mobile Thoroughbred
mobile Celeron vs mobile Appaloosa

My estimates of peak speed grades at end of 2002:
Northwood - 2.667 GHz 133/533 MHz FSB
Clawhammer - 2.6 GHz 200/400 MHz FSB
desktop Barton - 2.333 GHz 167/333 MHz FSB
desktop Thoroughbred - 2.0 GHz 167/333 MHz FSB
desktop Tualatin - 1.4 GHz 133 MHz FSB
desktop Appaloosa w/128K L2 cache - 1.6 GHz 133/266 MHz FSB
desktop Celeron - 1.0 GHz 100 MHz FSB
desktop Appaloosa w/64K L2 cache - 1.2 GHz 100/200 MHz FSB
mobile Tualatin - 1.4 GHz 200 MHz FSB
mobile Barton - 1.667 GHz 167/333 MHz FSB
mobile Thoroughbred - 1.5 GHz 167/333 MHz FSB
mobile Celeron - 1.0 GHz 100 MHz FSB
mobile Appaloosa - 1.1 GHz 100/200 MHz FSB



To: fyodor_ who wrote (37537)4/27/2001 3:32:16 AM
From: PetzRespond to of 275872
 
One point that hasn't been made of the new roadmap, is that, for the first time, AMD has committed to TWO 0.13 processes -- a Bulk Silicon process for Athlon derivatives and an SOI process for Hammer.

This is a lower risk approach than trying to do all on SOI. WATSONYOUTH commented on it as being risky if there was no NON-SOI process.

Once the decision was made to have two processes, the only question was whether to try to bring them up simultaneously. They decided that they might not have the manpower, or the capital to do it that way. And the delay in the Hammer family will give them enough time to come out with their own chipset, and do it right.

Petz