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To: Tenchusatsu who wrote (133478)	4/27/2001 2:57:54 PM
From: Scumbria	Respond to of 186894

Ten, The limitations to increasing the pipeline are: 1. latch delays (like you said) and 2. clock skew. Intel has done a lot of work to mitigate clock skew, and I would assume also minimize the latch delays. The main part of the P4 pipeline is 400% as long as the equivalent part of the Athlon pipeline, yet the speed delta is less than 33%. The ratio is severely out of whack. I have no inside info, but my speculation is that the 2-cycle cache and double speed ALU are the main speedpaths. Scumbria