Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Intel Corporation (INTC) -- Ignore unavailable to you. Want to Upgrade?

To: Tenchusatsu who wrote (133763)	4/30/2001 11:32:58 PM
From: pgerassi	Read Replies (2) \| Respond to of 186894

Dear Tench: Have you ever seen the HyperCube design? Cache Coherency can be achieved if every read transaction to remote memory is controlled by the remote NB. A write is the only thing that causes the caches to become incoherent. Either a read is taken as a snapshot at the time of the read (many systems are this way), notification is sent to all interested parties during a write (this could be done with a routine in the local CPU), or all remote reads are uncached and thus done each time (this is how I/O systems are always handled anyway like in PCI). It is up to the OS designer how this is handled. NUMA architectures are the wave of the future as local memory becomes far less latent than remote memory. Since memory densities will probably increase far more slowly, latency will be the bottleneck and local memory will become yet another cache level (It is referred to as L3 in some memory benchmarks). BTW, LDT has been renamed HTT. Pete