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To: dale_laroy who wrote (38303)5/4/2001 11:04:12 AM
From: fyodor_Read Replies (1) | Respond to of 275872
 
Dale: I have little doubt that they will not only shrink the gate lengths, but also implement low-k dielectrics, even if they can not shrink the process below 0.18-microns.

I believe AMD has stated that the current equipment at Fab25 would be able to handle .15µ. Now, wouldn't it make sense to convert everything to these process rules, if AMD has decided not to install new equipment? (i.e. if you're going to keep the equipment for a really long time, it would make sense to do a lot more to optimize for that equipment than if you were planning on upgrading in the near future).

I would agree that the extra speed isn't particularly needed at present, but that could well change at some point in the not too distant future. Additionally, there's the die size advantage to be gained. (and if you were going to go with low-K dielectrics, it would make sense to do that at the same time).

-fyo