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To: Dave who wrote (72115)	5/6/2001 12:10:47 PM
From: Harvey Allen	Read Replies (2) \| Respond to of 93625

This the one? Apparatus and method for bus timing compensation Programmable Delay Mechanisms for Device-Induced Timing Variation The present invention also uses multiple programmable delay mechanisms inside the device that match with internal device delay components to allow fine grain timing control. An example of this is the control of column read latency. The column read latency in the memory core, tCAC, comprises two components originating from different parts of the column datapath: tCLS and tDAC, as FIG. 14 shows. tCLS is the delay between the rising edge of COLLAT, when the column address is latched into the core, and the rising edge of COLCYC, when the column access begins and data is accessed from the sense amps in the core. These two delays can vary from device to device, depending on process variation, circuit design, supply voltage, and operating temperature. 164.195.100.11