Hi cordob; What is mentioned in the patents is not generally what is implemented in Rambus' designs. I guess that the primary reason for this is that the patents are lagging indicators...
I'll look around for some references to how the Rambus RSL bus is implemented in the PC.
That part of Intel went DDR while the other part went RDRAM is no surprise, and it is due to different management chains of command more than the technology facts. Large size RDRAM systems need a special sort of buffer which essentially splits a single channel into two. It has an amazingly small pipeline delay, 1 (400MHz?) clock each way, for a total of two clocks, if my memory serves. I'll dig up the Intel spec sheet if you want. The part would have application only in systems with more than the usual desktop number of DIMMs, except that Rambus was unable to get their channels to work with 3 DIMMs.
As far as RDRAM in mobile, if you listen to Rambus, they will explain that RDRAM uses much less power than SDRAM or DDR. Despite this "fact", DDR looks to hit mobile computing first.
AMD will put RDRAM onto its roadmap about 3 to 6 months after never. You earlier posted (somewhere) that you expected AMD to announce an RDRAM chipset by the end of the year. I put the post into my "to reply" subfile, with December 31, 2001 as the date, and around that time I will remind you of your (failed) prediction.
Re: "If AMD believed they would never catch up with Intel on the bandwidth question, ... they would have prepared for it." I'm not sure how to interpret this statement.
I'm guessing that you are under the impression that the only way to get high bandwidth is through RDRAM, and this is why you can't figure out why AMD hasn't pushed into the technology. I don't know how to approach a discussion on this because I don't know how you came to this conclusion, if you did. The alternative way to achieve high bandwidth is by increasing pin count. DDR samples are already shipping with 600MHz data rates and x32 bus widths. These chips provide considerably higher bandwidth than anything shipping or sampling from Rambus, but they do require more pins.
But pins are cheap now. Pins used to be connected to pads through "bonding wires" which were robotically connected at the factory. Back in those days, engineers had to scrape for every pin, but modern technology allows a full wafer of chips to have their bonding connections attached in a single operation. Costs per pin have fallen through the floor. Bandwidth per pin is no longer the big deal that it was 10 years ago. If it were a big deal, the memory makers would be putting together a royalty free standard that would provide higher bandwidth per pin. I guess they are doing that, but they don't need it right now because the explosion in packaging has ameliorated the pincount problem. Nowadays, most of the reason for keeping pincounts down is to save on board real estate or layers, but Rambus does not provide a solution that does this better than the competition. (See #reply-13485509 for an example of RIMMs vs DIMMs) That RDRAM doesn't provide a better use of board real estate is obvious if one simply looks at the traces in an i820 motherboard:
See the routing on an i820 RDRAM mother board, with notes provided by Bilow. These notes are for the i820 Chipset Design Guide Book. A perusal of this document leads to some fascinating insights into how RDRAM is actually used, and I think the technically inclined will find it fascinating reading: #reply-13678896
Anyway, here's a few links that will stun engineers who've been away from the industry for a while:
Good introduction to modern surface mount technology:
surfacemountcouncil.org
Great link from Altera with lots of information, plus links to more good stuff. Of particular interest is the chart "IC Package Type Usage" which shows IC packaging types and quantity production between 1980 and (estimated) 2005. When Rambus started, the cheap new technology for high pin density, BGA, was still 5 years in the future. But this is easily the fastest growing package type, and it is what has largely eliminated the market for Rambus' technology:
altera.com
Xilin packaging options:
xilinx.com
LSI-Logic's flip chip BGA family (from 1999, this is now standard technology):
lsilogic.com
Some links showing pricing for stuff in high pincount packages. (Obtained by google searching for "pricing" and "FBGA" or "BGA", "pricing" and "volume".) Of course these prices include the circuitry as well as the package, but they give a strict upper limit on the packaging costs. But what these prices should make clear is that the phrase "popcorn logic" now includes stuff in package sizes up to around 100 pins.
The GDX160VA is offered in a 208-pin plastic quad flat pack (PQFP), 272-contact ball-grid array (BGA) and an advanced 208-ball fine-pitch BGA package. Pricing in high volume starts at $7 each.
siliconstrategies.com
altera.com
actel.com
biz.yahoo.com
latticesemi.com
I know that Rambus lovers believe that their technology has no disadvantages, but besides the royalties it is a difficult solution to a problem that can be solved simply with cheap pins. The above should give an idea of just how cheap those pins have become.
Rambus is difficult to work with. When you have a bus that you can't hook a logic analyzer up to, it makes it difficult to figure out which component is causing a problem. All you can tell is that the sytem is failing, not which part. Here's some commentary from early on in the Camino fiasco:
EETimes, May 28, 1999:
...
"The current [A1 version of] Camino has problems," said one Taiwanese engineer. "Now, it's hard for us to say if it's a core-logic problem, a Rambus memory problem or our board design. Hopefully the next iteration of Camino will work when we get it at the end of May. It usually takes a couple of revisions to get a working motherboard. RDRAM boards may take up to four revisions, though."
Another problem with the Rambus transition is the high cost of logic-analyzer equipment Rambus requires. In late April, Hewlett-Packard Co. staged demos here of its HP16700A and HP16702A logic analyzers geared to address testing issues with Rambus. The systems cost about $230,000.
"The cost is just too high for our company," said one R&D engineer. "We currently aren't using a logic analyzer for our RDRAM boards."
"We will let Intel solve the logic-flow problems," another engineer said. "We will concentrate on EMI and signal-quality issues of the board. For those problems, we have purchased a high-speed oscilloscope.
...
eetimes.com
Here's what Tektronix has to say about the stuff. Can you read between the lines?
Examining Rambus® Technology
... Although Rambus systems eliminate the memory access bottleneck, they operate at the fringes of digital performance capability. ... While offering many advantages, the Rambus memory architecture creates three major system design and verification challenges for the system developer. ... This streamlined structure makes it complicated to examine real-time system interactions with a scope or logic analyzer. ... The logical signals used in the Rambus Channel pose some new requirements for the system designer due to their small logic swing and fast transitions. ... With information moving at this rate, there is little margin for error. ...
tektronix.com
The question that the industry asked itself in late 1999 is "Why should we use Rambus products when (1) it's difficult to use, (2) we would have to pay a royalty, (3) pins are cheap, (4) single direction buses like AMD's hyper transport are easier, and (5) we don't like Rambus' inability to tell the truth, nor their silly claims to have invented SDRAM.
-- Carl |
