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To: Bilow who wrote (72282)	5/8/2001 5:06:19 PM
From: Bilow	Respond to of 93625

Hi all; Here's a link from Micron which states (on page 47) that DDR uses less power than RDRAM, and then shows how the calculations are made over the next few pages: images.micron.com -- Carl

To: Bilow who wrote (72282)	5/8/2001 8:11:07 PM
From: gnuman	Read Replies (1) \| Respond to of 93625

Carl, re: RSL bus. Ignoring ptnewell's input. Here's my uneducated take on the bus. Secondly, since the RSL bus is not a CMOS bus, using a formula for CMOS power dissipation is inappropriate. In particular, the RSL bus has pull up resistors that dissipate continually whenever a "1" is applied. This means that there is no frequency dependence at all in that part of the power consumption, and the CMOS power equation is entirely unsuitable. The bus is a strip or microstrip line with one termination resistor per line. (28Ohm). (The bus pull up). The termination resistors are connected to Vterm of 1.8V. There is no power dissipation on the bus when quiescent or when the output is in the "zero" state. The signals are referenced to Vref of 1.4V. Logic "one" is 1.0V. (Note that power can be pattern sensitive). The swing is from 1.8V to 1.0V, or 800mV. I agree the CMOS power equation doesn't apply to power on the RSL bus. The voltage swing in RDRAM is 0.8 volts, taken in two steps of 0.4 V. I believe there is just the 0.8V step when asserting a "one." I think the idea of two 0.4V steps comes from confusion of Vref. Vref is used to provide a quasi-differential signal around the 1.4Vref on the controller. As for voltage steps on the bus, I think there are only two. (But I think that's also one reason a current source is used). And if you look at the bus at the controller pin, the eye will be uniform in amplitude irrespective of where the signal originated on the bus. JMO's