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To: Bilow who wrote (72401)	5/9/2001 7:02:59 PM
From: gnuman	Respond to of 93625

Carl, re: The third step doesn't appear at the controller, it appears at the second RDRAM output, the one that took over driving a '1' from the first one. Did you read my last post? If there is no overlap, when one source releases the other takes over. There may be some very narrow spikes at the source dependent on timing, (and I think they factored in delays so this won't happen), but I sure don't see any third level. Again, you need to look at the timing diagrams to see just what happens with consecutive "ones." For all I know, the bus returns to logic "zero" between reads. If that's the case just reverse the process. The bus steps to 1.4V and returns to 1.8V after the wave transit. The impedances never change with time on the RSL bus. Maybe I'm not explaining it right for you. When the source turns on what does it see? It sees a characteristic impedance of 28 Ohms in both directions, or Zo/2. (Maybe an easier way for you to think of it is a current source driving two strip-lines in parallel, half the current going into each line). That's the reason the voltage initially swings to only 1.4V. (Or a 0.4V signal). When the wave returns past the source what does it see? It sees a high impedance in the controller direction, and 28 ohms in the termination direction, (or Zo), and the voltage swings to 1.0V. So the impedance the source sees changes with time. Since you're interested in the waveforms at various sources on the bus, that's what you need to factor in. You've already admitted that you're rusty on the subject. That's for sure. What's your excuse? <VBG> JMO's