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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Bilow who wrote (72418)	5/10/2001 12:38:03 AM
From: gnuman	Read Replies (2) \| Respond to of 93625

Carl, re; RSL. I looked at your "step" diagram, (the last one). I think I need to understand the electrical length of the bus, the length between the first source and the controller, the length between the last source and the termination, the width of the signal, etc., etc.. Also the programmed chip read latency corresponding to the position of the chips on the bus. (Done at initialization). I take that back. I don't want to know anymore about this bus. You can have three steps, four if you like. <g> You realize, of course, there are a bunch of Rambus design engineers laughing their arses off over this series of posts. <VBG> Gene

To: Bilow who wrote (72418)	5/10/2001 11:20:52 PM
From: gnuman	Read Replies (2) \| Respond to of 93625

Carl, re:The total length of a fully populated 2-RIMM RSL bus, with two 16-RDRAM RIMMs installed is in excess of 4ns. Regarding your timing analysis diagram, assume: - Bus is populated as above. - Distance between first and last chip on the bus is 2.5ns. Excludes bus length to controller and to terminations. (And an easy number to work with. <g>). - Address and control propagate away from the controller toward the termination end. - Read outputs propagate toward the controller end. - Data rate 800MHz, (1.25ns cycles) - Data width 1.25 ns. If that's all there was to analyze you've got some real system problems. For example, assume consecutive reads of last chip, first chip. (N32, N1). Using the above assumptions, looks to me like N32 will appear in reverse order long after N1. <g> The solutions to this problem are probably very interesting and probably need to be known for a thorough analysis of RSL signaling. At any rate, we know the solutions were found and that there can be consecutive data at 800mHz. As I mentioned in an earlier post, there is probably jitter, (I think controlled to <10%), but for purposes of my question let's assume there is none. So what we have is consecutive 1.25ns wide data at 1.25ns cycles flowing on the bus and into the controller without overlap. So the question is, if there is no overlap of data flowing on the bus, how can there be overlap at the data source on the bus? TIA