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Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: gnuman who wrote (72571)	5/11/2001 5:49:55 PM
From: Bilow	Respond to of 93625

Hi Gene Parrott; That link pretty much tells the story, I think. On page 8 of 15, it reads: "Conventional DRAMs require that one device stop driving the bus before another device can start, effectively causing a one clock cycle delay for bus turn-around. In 100MHz SDRAM systems, this change in Read/Write direction causes a 10ns clock cycle of delay. In contrast, a one-clock delay in the Rambus system is only 2.5ns." Note that they do not admit that it is possible to switch from one driver to another with only a one clock delay. If they want to avoid the 3rd step, the delay will have to be longer. This is a retreat from the original spec for the RSL channel, and I believe it was made in order to avoid the 3rd step. The other passage of interest is on page 3: "Also due to the topology of the Channel, write data can be sent down the Channel in the next clock cycle following a Read transaction. As soon as the Read data reaches the controller, it can issue the Write data without delay." This is equivalent to my note that the 3rd step only shows up if you transfer control from a near RDRAM to a farther out RDRAM. (This is since a controller WRITE is equivalent (in terms of electrical activity &c.) to an RDRAM READ with the RDRAM chip stationed at the controller position.) It continues (again on page 3): "However, a write followed by a read transaction must wait a short delay, equal to the round-trip length of the Channel. For short Channels, this is only one Rambus clock cycle, 2.5ns. For the longest Channels, the delay could be five clock cycles, or 12.5ns." Since the WRITE data is going to all be eaten up by the termination resistor anyway, and only goes down the bus once, it would be possible to arrange for READ data to arrive at the controller just after the last of the WRITE data left the controller. But to do this, the READ output would have to be turned on during the middle of the WRITE sequence, (because of the delay to get to the controller), and this means that the 3rd step would appear. -- Carl P.S. Another place to look for the intention and what actually got implemented is recent Rambus patents. As I mentioned on this thread (and was seconded by Monohan during the trial) the original Rambus patents do not cover modern (i.e. Direct) RDRAM, as the pin count of the bus as defined in the claims explicitly excludes RDRAM.