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Politics : Formerly About Applied Materials -- Ignore unavailable to you. Want to Upgrade?

To: Math Junkie who wrote (46616)	5/11/2001 6:01:08 PM
From: TimF	Read Replies (1) \| Respond to of 70976

Seems like all these ratings and targets on equipment stocks are just made from whole cloth. Is that any different then ratings and targets on other types of stocks? Tim

To: Math Junkie who wrote (46616)	5/11/2001 9:46:42 PM
From: Proud_Infidel	Read Replies (1) \| Respond to of 70976

Intel aims research fab at 'pathfinding' 300-mm processes into production By Mark LaPedus Semiconductor Business News (05/11/01 17:34 p.m. EST) HILLSBORO, Ore. -- Leave it to Intel Corp. to refine the way 300-mm wafer technology is brought into production. Today, the world's largest chip maker told the press that it is applying a new "research & pathfinding" approach--instead of the usual R&D--to bring the larger wafer diameter into volume production. Intel officials also today gave the press a grand tour of the company's new $250 million "R&P" facility here, which will be dedicated strictly to 300-mm research and "pathfinding," meaning it will play an ongoing role in bringing new processes to production fabs during the rest of this decade. The Hillsboro facility, called RP1, is adjacent to Intel's D1C development fab, which has produced the company's first 0.13-micron chips on 300-mm wafers (see April 2 story). The D1C facility will eventually move into "partial" production during early 2002 using the 0.13-micron process. Intel officials today said the D1C fab will also start up a next-generation 0.10-micron (100-nm) technology during the second half of 2002. That process, called P1260, is a copper technology, capable of supporting six layers of metal interconnect. In 2002, Intel plans to transfer the 0.13-micron process to its first dedicated 300-mm production facility, called Fab 11x (for Fab 11 expansion), in Rio Rancho, N.M. Intel announced the 300-mm facility a year ago, setting the plant's budget at $2 billion (see May 24 story). Meanwhile, the new RP1 facility will tackle other processes as time goes forward, said Tom Garrett, Intel's 300-mm program manager. The facility has 56,000 square feet of cleanroom space for creation of new 300-mm process modules, which will be transferred into Intel production facilities over the next 10 years. According to Intel officials, the task of research and "pathfinding" is different from the role of development fabs in that R&P is more focused the key "cross-over" phase between research & development. Intel said RP1 will allow engineers to share 300-mm wafers between research and development projects in order to "accelerate the introduction of advanced technologies for high-volume plants." "RP1 represents a unique capability in the industry," said Gerald Marcyk, director of Intel's Components Research Group. "We can conduct research both on a small scale in beakers and at a large scale using batches of 300-mm wafers -- all in one lab." The RP1 facility will also be the home of Intel's first 157-nm and extreme ultraviolet (EUV) lithography tools, said officials today. A source said Intel now expects to receive the first 157-nm lithography system from a U.S. vendor--Silicon Valley Group Inc.--during the summer, which is about nine months later than expected. The 157-nm tool will be used to develop Intel's first 300-mm processes for the 0.07-micron (70-nm) technology node. This technology, called P1264 by Intel, will have 0.035-micron (35-nm) gate lengths. It is now due to be ready for production in 2005. Intel is planning to use EUV lithography for the 0.05-micron (50-nm) technology node, which is expected to hit production in 2007. This technology, called P1264, will have transistor gates measuring just 0.025 micron (25 nanometers), according to Marcyk. "The 157-nm lithography technology will be ready before EUV, which will not be used until the second half of the decade," he told journalist today. The RP1 facility will also be the home for Intel's development of 300-mm technology for the 0.035-micron (35-nm) technology node, which will have transistor gates measuring just 15 nm. Other technologies, such as the mixture of copper interconnects and optical links on chips, will be pursued in RP1, said officials today.