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To: Robert Salasidis who wrote (134796)5/14/2001 1:29:24 AM
From: pgerassi  Read Replies (1) | Respond to of 186894
 
Dear Robert:

On the P4 it is a penalty. Heck, on P4, shifts and rotates are penalized greatly (why someone would leave out a barrel shifter in a modern GP CPU is still stupid to me). On a 386 or smaller, it was a whole lot faster than a software subroutine would do it (and a lot smaller to).

As far as large file support, are you forgetting that CPUs can execute millions of instructions for each disk access? A 10 cycle penalty is nothing at all. Furthermore, you can use the demand paging virtual memory hardware to speed this up with a good design (Linux shows this), and its included with all 32 bit x86 systems.

The problem for Itanium is that VLIW IA-64 compilers are still not very good and show poor performance. Coding is assembly is required to get good performance out of Itanium. It is still expensive to code in assembly. So you have a choice, high cost high performance, or low cost mediocre performance (from a software development standpoint). Your large files argument shows that you would opt for the latter and many would do so, if they had those choices. But, they have a choice of high performance low cost from the x86 world and the 64 bit RISC world. Total system costs would be lower for the last two (sometimes by enormous amounts).

All in all, 64 bits is good, Itanium's version is bad. HP may be able to solve this with McKinley but, without further info as to what they did different, its impossible to tell, if they did or not. x86-64 is a much easier upgrade and keeps terrific 32 bit performance to boot.

Pete