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Technology Stocks : Advanced Micro Devices - Moderated (AMD) -- Ignore unavailable to you. Want to Upgrade?

To: dougSF30 who wrote (39670)	5/14/2001 5:54:25 PM
From: combjelly	Respond to of 275872

"And somebody pointed out that the point-to-point bus may obviate the usefulness of a > 256Kb L2" That'd be me. I am dubious that a 1 or 2 meg. cache would be worth the extra die space/possible restrictions on clock rate/lower yield that it would cost for use with EV6. I can see going to 512k if an inclusive cache were used. An inclusive cache might have some advantages in reducing the congestion due to the traffic between the L1 and L2 when data is evicted, and the simpler circuitry might help with raising the clock rate. But the cost of a larger than 256k or maybe 512k cache in 0.18 micron would not be worth it, IMHO. Sure, crank it up a little at 0.13 and 0.10 micron, but for current design rules? Some of the other different signals might include pins and support circuitry for reliability and server management for servers and workstations. I suspect that some of the time that resulted in slippages was to work out these functions into modules so that they can be mixed and matched. Hmm, this also opens the possibility that AMD might be able to offer some degree of customization for large OEMs for servers and workstations... That does play to AMD's advantages, they have a long history of making on the fly changes, while Intel focusses more on refining their process to squeeze every last die out of a wafer. The big difference between a cell-based approach, and the "individually, hand-crafted transistor" approach. Yeah, I know that Intel doesn't really optimize every single transistor.