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To: Ali Chen who wrote (42753)	5/17/2001 5:16:47 PM
From: tinkershaw	Read Replies (1) \| Respond to of 54805

Ali, Kind of funny if all the major elements of Rambus inventions were created much earlier why the issue of "prior art" has never been put forward at trial nor has lack of novelty or obviousness been an issie. They certainly were not a part of the Infineon trial, it is not much if any part of the Micron trial. I hear all the time about how obvious everything was that Rambus invented yet I find a surprising lack of prior art on the topic. I was also very intrigued of how Infineon over a period of 3 years kept asking Rambus for more and more information about their inventions, even after Rambus basically said, "look, buy it or we shall stop sending you specs." At trial it came out this was because Infineon largely lacked any in-house IP regarding the creation of SDRAM, they were desperate for the help. Also in regards to the Infineon suit. There are many justifiable rationale why Judge Payne may have decided to to limit the interpretation of Rambus patents so narrowly. Perhaps it has something to do with the history of the patent and how it was obtained. I don't know, and I am unaware of any evidence brought up at trial or in the Markman ruling which indicated that this was the basis of Judge Payne's decision. However, looking at the law on the topic, absent these "file wrapper" elements, Judge Payne's interpretation and limitation of scope of Rambus patents to a multiplex bus seem (and this is just general law, applied generally to the Judge Payne's Markman decision, as I was not there and I do not know everything in the history of the patent file and I don't know what exactly Judge Payne used as his rationale), but in general, it is well established that the scope of a patent cannot be limited either by the "preferred embodiment" of the patent nor can it be additinally limited from making inferences from the specifications of the patent. Absent some file wrapper element with Rambus' patents there is a very good chance the Markman rulings will be overturned on appeal. As absent these file wrapper elements it seems clear that Judge Payne did just these two things in his Markman opinion. If other factors were not at work, this was an erroneous decision by Judge Payne. Until such a ruling is finalized on appeal I'll withhold my discussion of who invented necessary and fundamental elements that are involved with the current generation of SDRAM and DDR technologies. In regard to the fraud element I'm still a bit perplexed with the decision the jury came to. I honestly don't exactly know what they based their decision on. Nevertheless, it is evidence that anything can happen when you get in front of the jury. I don't know what the chances are on appeal with the fraud count, and won't know until I give it a much deeper look to figure out exactly what happened on that count. Tinker

To: Ali Chen who wrote (42753)	5/18/2001 6:56:17 AM
From: John Walliker	Read Replies (1) \| Respond to of 54805

Ali, Scalable Coherent Interface, published in 1988: slac.stanford.edu It contains all relevant ideas about Dual Data Rate, packet protocols, and current-steering drivers. Control registers were invented much earlier. It is important to recognise that what is described in this paper is very different from Rambus - and from SDRAM or DDR. In particular, the paper discusses a proposed communications system that would use multiple point-to-point links. It states that the authors do not believe that much further progress can be made with bus type structures. The current steering drivers that they suggest are totally different from the "constant current" drivers used in Rambus. Some of the physical limitations to performance of bus sytems which they list have been overcome by Rambus. The paper is well worth reading to gain an appreciation of the state of the art in 1988 and to understand the magnitude of the innovation from Rambus. It is also important to note that the paper does not describe an implementation, but a set of ideas for future development. Were these ideas ever converted into a successful product? John

To: Ali Chen who wrote (42753)	5/18/2001 7:18:03 AM
From: John Walliker	Read Replies (1) \| Respond to of 54805

Ali, Currently Intel holds a patent that seems to be closest to current Rambus implementation: delphion.com US6173345:Method and apparatus for levelizing transfer delays for a channel of devices such as memory devices in a memory subsystem Hope it clears some confusions between patents and reality. The following text is from the patent you refer to. It makes it quite clear that the patent refers to a more efficient way of implementing the initialisation algorithm than that used hitherto. It refers to Rambus data sheets. The inventors do not claim to have invented the scheme used by Rambus, but to be enhancing it. " A Rambus (TM) Direct Rambus Dynamic Random Access Memory (Direct RDRAM) bus is one example of a bus which utilizes memory devices along a channel. It is known that a Direct RDRAM Memory Controller (RMC) may expect to receive data from all devices along a channel during a particular bus cycle. In fact, a controller, described in "Direct RMC.d1 Data Sheet" available from Rambus Corporation of Mountain View, Calif., provides a controller delay register to assist in levelizing delays. Additionally, one or more delay registers may also be provided within individual RDRAM devices (e.g., a TRDLY register discussed in the Rambus "Direct RDRAM 64/72-Mbit" Data Sheet at p. 36). Values may be stored in these registers in order to equalize delays between the various devices along the channel. Typically, the controller delay value is initialized first, then the delay values for individual memory devices are adjusted. The prior art may not provide a mechanism to reduce the number of cycles performed during initialization. In general, the prior art may not specify particular ways to test only a subset of the total number of possible delay values. The prior art also may not specify a method of choosing initial values for certain delay testing iterations, an efficient order for testing delay values, a method for performing each test, or a way of aborting delay testing and disabling devices when certain values are reached. Thus, the prior art may not provide an adequate method for levelizing delays along a channel of devices. " John