Silicon Investor (SI) -- The First Internet Community

STOCKTALK

We've detected that you're using an ad content blocking browser plug-in or feature. Ads provide a critical source of revenue to the continued operation of Silicon Investor. We ask that you disable ad blocking while on Silicon Investor in the best interests of our community. If you are not using an ad blocker but are still receiving this message, make sure your browser's tracking protection is set to the 'standard' level.

Technology Stocks : Rambus (RMBS) - Eagle or Penguin -- Ignore unavailable to you. Want to Upgrade?

To: Jdaasoc who wrote (73448)	5/22/2001 12:51:59 PM
From: Win Smith	Read Replies (1) \| Respond to of 93625

Where, exactly, was I "completely wrong" about what a XEON chip is? It's got 180 more pins than the P4 and 2-way SMP capability. What did I miss? The Piii Xeon still ships in 256k cache versions, why do you hypothesize that the same won't hold true for the P4 version in the future? Which is about what would be necessary for my currently true statement to "forever be false". Intel might raise the minimum cache to 512k for both versions with the .13um shrink, but that wouldn't exactly improve the truthfulness of your grandiose pronouncement. Having followed certain local Intel engineers and their endless "We will bury you" proclamations about AMD on SI over the last couple years, the rest of your post is not exactly unfamiliar in content and believability. I'd guess the droids are in general all perfectly happy to see Intel continue to profess fealty to the bus people.