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To: Bilow who wrote (73598)5/24/2001 8:44:02 PM
From: Win Smith  Respond to of 93625
 
Funny thing, Carl. When Intel finally ships a DDR chipset, I imagine the P4 may look pretty good with it. If DDR can do a long enough burst, a standard 64 bit DIMM memory system could fill the P4's 128byte cache line with the same timings as SDR SDRAM fills the Piii 64 byte line. Intel could probably do a 128bit wide memory system easily enough too, at least as cheaply as the dual channel RDRAM system, but never mind that.



To: Bilow who wrote (73598)5/24/2001 10:16:21 PM
From: Jdaasoc  Read Replies (2) | Respond to of 93625
 
carl:
they're going to do exactly what they did with PC133, deny that the stuff is stable, at least publicly

You write in so much intrigue and deceit that doesn't exist. Intel said no such thing. They actually said that they would support PC133 once they adjusted some of the specifications in the standard to their liking. Do you not acknowledge that Intel had just about final say on standards for PC66 PC100 and PC133. What must irk you the most is that they have been forcing RDRAM down the reluctant industrys throats for several years.

By the way, can you show me a Sysmark 2001 score of greater than 199 that a pre-release dual XEON 1.7 system just posted. The best AMD Athlon could do was 139. BWAHAHAHAHAHA

www.anandtech.com

I been trying to get to that website tonight and I get no repsonse. I guess the Intel powers that be don'r want people to know the truth about blinding XEON speed otherwise Intel may lose 20-30% of their CPU business for a month waiting for it if erveryone knew how fast the XEON systems were.

john

PS When I login and find 8 items in my inbox I know that some of them must be from you carl.