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To: Harvey Allen who wrote (43315)	6/8/2001 1:22:35 AM
From: THE WATSONYOUTH	Respond to of 275872

I.B.M. Finds Way to Speed Up Chips By BARNABY J. FEDER I.B.M. plans to announce today that it has figured out how to stretch silicon during standard semiconductor manufacturing, a development that is expected to allow it to start making faster, less power-hungry versions of a wide variety of microchips within two years. I.B.M. said the advances it had developed reduced resistance to electrons flowing through chips enough to bolster processing speeds up to 35 percent. While I.B.M.'s research has concentrated on processors used in computers, the power- saving potential of the new technology may be attractive to manufacturers of cellular phones and other devices that use microchips that amplify signals. "The real breakthrough is that we are using conventional manufacturing technology," said Randall D. Isaac, I.B.M.'s vice president for science and technology. Researchers have known for decades that electrons will move more freely through semiconductors if the lattice of atoms that make up such crystalline materials can be stretched without breaking any bonds. Stretching also lifts the performance of circuits formed out of negatively charged holes created by the absence of electrons, though not as strongly. But the only chips demonstrating the benefits of what is known as strained silicon had been made in academic labs one at a time or from highly specialized materials. One reason progress had been slow was that many chip makers thought the performance benefits of strained silicon would be overwhelmed by other forces as the distance between transistors shrank with each new generation of chips. Now, analysts said, they expect several other chip manufacturers to rush to catch up. "This is likely to lead people at companies like Motorola and Texas Instruments to dust off projects they have had on the back burner," said Richard Doherty, president of Envisioneering, a technology research company in Seaford, N.Y. Before I.B.M. offers commercial quantities of strained silicon devices to its hardware divisions and outside customers, it must improve the yield of defect-free chips from the new process, said Bijan Davari, vice president for semiconductor development for I.B.M.'s microelectronics manufacturing group. Dr. Davari said researchers were also working on ways to bring the performance of the hole-based circuits more in line with the electron- based circuits because many chips use combinations of the two. I.B.M.'s chances of success are good, analysts said, based on its strong track record in recent years of bringing innovative microchip design and processing advances to market a year or more sooner than competitors. I.B.M.'s strategy has been to trail companies like Intel as closely as possible in rolling out smaller transistors — the industry's main path to improving chip performance — while trying to lead the way in finding new materials or packaging designs that improve the performance of those smaller chips. "They are rolling out stuff with amazing regularity and far ahead of everyone else," said Frederick L. Zeber, president of Pathfinder Research in San Jose, Calif. To master strained silicon, I.B.M. took advantage of the expertise it has developed in the last decade with silicon germanium, a high-performance variation on standard silicon that has a slightly more spacious crystalline structure. By tinkering with its processes for depositing thin layers of silicon on the silicon germanium, I.B.M. managed to get the atoms in the silicon crystal to spread apart into a closer alignment with the silicon germanium. The process stretches the silicon lattice less than 1 percent, but that is enough to increase the mobility of the electrons 70 percent, according I.B.M.'s researchers. I.B.M. said it had also been able to combine its method for producing strained silicon with its previously announced technology for inserting a thin insulator under the crucial processing elements of a chip. That technology, known as S.O.I., for silicon- on-insulator, also speeds up chip performance and reduces power needs. I.B.M. researchers will present papers describing the strained silicon results and its ability to combine the two technologies at a conference next week in Kyoto, Japan. nytimes.com Interesting stuff. But I have doubts of the VLSI potential of the strained material. The extreme low temperature epitaxial deposition of these strained Si/Ge layers is a non equilibrium process. The defect densities are quite high....certainly not low enough for VLSI. You may note that all current Si/Ge BiCMOS processes currently offered have very limited amounts of bipolar requirements. With bipolar requirements in these communication chips of less than a few hundred thousand devices, a high defect density is not a concern. The Si/Ge layer becomes poly over oxide and functions as the gate of the CMOS part of the BiCMOS process. Thus, the amount of CMOS is not limited since the channels of the CMOS devices are still built in the bulk material. What is claimed here is that the CMOS channel will be in the strained material and I would expect defect densities to be a great concern. But, give those guys some time and a goal, and they will eventually get it. You can bet on it. THE WATSONYOUTH P.S. Randall D. Isaac, I.B.M.'s vice president for science and technology. He hired me into IBM and was my first boss.... a very sharp guy. Bijan Davari, vice president for semiconductor development for I.B.M.'s microelectronics manufacturing group. I worked for him for years and he was at various times my 2nd, 3rd, and 4th level Mgr. Ghavam Shahidi, very recently named an IBM fellow and chief architect of IBM's SOI CMOS logic processes. He was my first level manager the last 3 years. Damn.....where did it all go wrong for me????