To: Charles R who wrote (43409 ) 6/8/2001 1:52:55 PM From: milo_morai Read Replies (2) | Respond to of 275872 <font color=blue>1 tip/chip tip/chip set for Hammer (name undecided and shipment timewise undecided) * HyperTransport interface * AGP 4x OR 8x * 32bitcPci * LPC interface * Ultra ATA/100 * IO/APIC * Serial ATA (channel 2) * 6 port USB (2.0 correspondences) * Hardware modem * LAN function (MII interface) * Power management function of advancement It is Athlon/Duron edition of the PL266 for the Pentium III/CELERON in regard to the KL266. The fact that we should observe, probably is tip/chip set for the Hammer. As with the road map of the VIA concerning the tip/chip set for the Hammer as description above, although this much function is actualized with 1 tip/chip, seeing, understood, the description regarding DRAM interface is not everywhere. As for being able to imagine from this case there is only one. In other words memory interface is to be integrated on CPU side. Besides the fact that as for Brown the AMD has recognized the fact that it has the plan such as that in regard to this case, as for the アンドリュー * phosphorus person of the ストラテジックマーケティングセンターマネージャ of the ALi answering to the interview of the writer, " the Hammer will support the HyperTransport, it is integrated on CPU side we will express memory interface, ", we probably will be possible to say almost you do not make a mistake about. There is a merit that it is possible, to lower the レイテンシ the between the CPU and memory, by integrating memory interface to CPU side, it is possible to improve the access speed to memory. However, in case of the system which supports the multiple processor like the Hammer, because the necessity to take consistency between the memory which is connected to each processor comes arising, it reaches the point where very wide bandwidth is required in the HyperTransport. Perhaps here how is solved, it becomes one of the technical point of the Hammer family. Translated from ragingbull.lycos.com